Patents by Inventor Yu-Hsiang Liao
Yu-Hsiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250040213Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.Type: ApplicationFiled: July 27, 2023Publication date: January 30, 2025Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Yi-Hsiang Chao, Peng-Hao Hsu, Yu-Shiuan Wang, Chi-Yuan Chen, Yu-Hsiang Liao, Chun-Hsien Huang, Hung-Chang Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20240379423Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20230411160Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.Type: ApplicationFiled: June 16, 2022Publication date: December 21, 2023Inventors: LI-WEI CHU, YU-HSIANG LIAO, HUNG-HSU CHEN, CHIH-WEI CHANG, MING-HSING TSAI, YING-CHI SU
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Publication number: 20230008239Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.Type: ApplicationFiled: April 12, 2022Publication date: January 12, 2023Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
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Patent number: 11309213Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.Type: GrantFiled: July 27, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Patent number: 11309217Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.Type: GrantFiled: March 1, 2018Date of Patent: April 19, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Patent number: 11222818Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.Type: GrantFiled: July 13, 2018Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
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Patent number: 11195791Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.Type: GrantFiled: December 9, 2019Date of Patent: December 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20200357691Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
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Patent number: 10727117Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.Type: GrantFiled: September 13, 2018Date of Patent: July 28, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Publication number: 20200111739Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.Type: ApplicationFiled: December 9, 2019Publication date: April 9, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20200020583Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Hsiang CHAO, Min-Hsiu HUNG, Chun-Wen NIEH, Ya-Huei LI, Yu-Hsiang LIAO, Li-Wei CHU, Kan-Ju LIN, Kuan-Yu YEH, Chi-Hung CHUANG, Chih-Wei CHANG, Ching-Hwanq SU, Hung-Yi HUANG, Ming-Hsing TSAI
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Patent number: 10504834Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: GrantFiled: March 1, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20190273042Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20190273024Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
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Publication number: 20190157141Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.Type: ApplicationFiled: September 13, 2018Publication date: May 23, 2019Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
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Patent number: 8581099Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board, each of the plurality of metal brackets defines a receiving space receiving a spring sheet. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board. Each of a plurality of ribbons is clamped between the spring sheet and a corresponding metal bracket, and the ribbon directly and electrically contacts the corresponding metal bracket.Type: GrantFiled: March 28, 2012Date of Patent: November 12, 2013Assignee: Ampower Technology Co., Ltd.Inventors: Chih-Chan Ger, Yu-Hsiang Liao, Shang-Ting Chen, Yun-Bing Wang
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Publication number: 20130014970Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board, each of the plurality of metal brackets defines a receiving space receiving a spring sheet. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board. Each of a plurality of ribbons is clamped between the spring sheet and a corresponding metal bracket, and the ribbon directly and electrically contacts the corresponding metal bracket.Type: ApplicationFiled: March 28, 2012Publication date: January 17, 2013Applicant: AMPOWER TECHNOLOGY CO., LTD.Inventors: CHIH-CHAN GER, YU-HSIANG LIAO, SHANG-TING CHEN, YUN-BING WANG
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Publication number: 20130016474Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board.Type: ApplicationFiled: March 22, 2012Publication date: January 17, 2013Applicant: AMPOWER TECHNOLOGY CO., LTD.Inventors: CHIH-CHAN GER, YU-HSIANG LIAO, SHANG-TING CHEN, TSUNG-LIANG HUNG
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Patent number: D778321Type: GrantFiled: October 13, 2015Date of Patent: February 7, 2017Assignee: Caterpillar Inc.Inventors: Emmanuel K. Techie, Samuel S. Kumar, Craig J. Szymanski, Chunsheng Li, Yu-Hsiang Liao