Patents by Inventor Yu-Hsiang Liao

Yu-Hsiang Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040213
    Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Hsiang Chao, Peng-Hao Hsu, Yu-Shiuan Wang, Chi-Yuan Chen, Yu-Hsiang Liao, Chun-Hsien Huang, Hung-Chang Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20240379423
    Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20230411160
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes an epitaxial structure and a metal silicide layer. The epitaxial structure includes a semiconductor material. The metal silicide layer is disposed on the epitaxial structure. The metal silicide layer includes the semiconductor material, a first metal material and a second metal material. An atomic size of the first metal material is greater than an atomic size of the second metal material, and a concentration of the first metal material in the metal silicide layer varies along a thickness direction.
    Type: Application
    Filed: June 16, 2022
    Publication date: December 21, 2023
    Inventors: LI-WEI CHU, YU-HSIANG LIAO, HUNG-HSU CHEN, CHIH-WEI CHANG, MING-HSING TSAI, YING-CHI SU
  • Publication number: 20230008239
    Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.
    Type: Application
    Filed: April 12, 2022
    Publication date: January 12, 2023
    Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 11309213
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 11309217
    Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 11222818
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsiang Chao, Min-Hsiu Hung, Chun-Wen Nieh, Ya-Huei Li, Yu-Hsiang Liao, Li-Wei Chu, Kan-Ju Lin, Kuan-Yu Yeh, Chi-Hung Chuang, Chih-Wei Chang, Ching-Hwanq Su, Hung-Yi Huang, Ming-Hsing Tsai
  • Patent number: 11195791
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20200357691
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
  • Patent number: 10727117
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Liao, Ya-Huei Li, Li-Wei Chu, Chun-Wen Nieh, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20200020583
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiang CHAO, Min-Hsiu HUNG, Chun-Wen NIEH, Ya-Huei LI, Yu-Hsiang LIAO, Li-Wei CHU, Kan-Ju LIN, Kuan-Yu YEH, Chi-Hung CHUANG, Chih-Wei CHANG, Ching-Hwanq SU, Hung-Yi HUANG, Ming-Hsing TSAI
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20190273024
    Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Publication number: 20190157141
    Abstract: A method for manufacturing a semiconductor structure includes following operations. A sacrificial layer is formed over the conductive layer, wherein the sacrificial layer includes a first sacrificial portion over the first conductive portion, and a second sacrificial portion over the second conductive portion, and a first thickness of the first sacrificial portion is larger than a second thickness of the second sacrificial portion. The first sacrificial portion and the second sacrificial portion of the sacrificial layer, and the second conductive portion of the conductive layer are removed, with at least a portion of the first conductive portion remaining over the bottom of the trench.
    Type: Application
    Filed: September 13, 2018
    Publication date: May 23, 2019
    Inventors: YU-HSIANG LIAO, YA-HUEI LI, LI-WEI CHU, CHUN-WEN NIEH, HUNG-YI HUANG, CHIH-WEI CHANG, CHING-HWANQ SU
  • Patent number: 8581099
    Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board, each of the plurality of metal brackets defines a receiving space receiving a spring sheet. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board. Each of a plurality of ribbons is clamped between the spring sheet and a corresponding metal bracket, and the ribbon directly and electrically contacts the corresponding metal bracket.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: November 12, 2013
    Assignee: Ampower Technology Co., Ltd.
    Inventors: Chih-Chan Ger, Yu-Hsiang Liao, Shang-Ting Chen, Yun-Bing Wang
  • Publication number: 20130014970
    Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board, each of the plurality of metal brackets defines a receiving space receiving a spring sheet. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board. Each of a plurality of ribbons is clamped between the spring sheet and a corresponding metal bracket, and the ribbon directly and electrically contacts the corresponding metal bracket.
    Type: Application
    Filed: March 28, 2012
    Publication date: January 17, 2013
    Applicant: AMPOWER TECHNOLOGY CO., LTD.
    Inventors: CHIH-CHAN GER, YU-HSIANG LIAO, SHANG-TING CHEN, YUN-BING WANG
  • Publication number: 20130016474
    Abstract: A photovoltaic junction box includes a housing, a circuit board received in the housing, a plurality of metal brackets, and a plurality of bypass diodes. The plurality of metal brackets are secured to the circuit board. The plurality of bypass diodes are respectively secured to the plurality of metal brackets and electrically connected to the circuit board.
    Type: Application
    Filed: March 22, 2012
    Publication date: January 17, 2013
    Applicant: AMPOWER TECHNOLOGY CO., LTD.
    Inventors: CHIH-CHAN GER, YU-HSIANG LIAO, SHANG-TING CHEN, TSUNG-LIANG HUNG
  • Patent number: D778321
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: February 7, 2017
    Assignee: Caterpillar Inc.
    Inventors: Emmanuel K. Techie, Samuel S. Kumar, Craig J. Szymanski, Chunsheng Li, Yu-Hsiang Liao