Abstract: A display device includes a display panel having a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a display phase of the pixel circuit for light-emitting and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit to generate a sensing voltage; a driving transistor for driving the diode during the display phase; a readout transistor, with a gate receiving the sensing voltage during the sensing phase to serve as a source follower; first to seventh transistors, gate control signals applied to the gates of the first to seventh transistors so that the pixel circuit switches between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase.

Abstract: The present invention relates to an image sensing device comprising: an image sensing array and an image processing circuit. The image sensing array includes sensing units, and the sensing units respectively generate multiple pieces of pixel data. The multiple pieces of pixel data are generated according to different frame rates under different exposure periods, and include a first pixel data of a first subframe and a second pixel data of a second subframe. The first pixel data is generated by exposing a first exposure period for a first frame rate, and the second pixel data is generated by exposing a second exposure period for a second frame rate. The first frame rate is less than the second frame rate. The first exposure period is greater than the second exposure period, and multiple pieces of the second pixel data are generated during one image capturing operation.

Abstract: An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.

Abstract: A light-emitting-diode driver structure applicable to driving a display panel and operation method thereof are provided. The LED driver structure includes at least one LED driving group, and the LED driving group is composed of a plurality of LED driving circuits which are serially connected in cascade. Each LED driving circuit of the LED driving group receives a data input signal in common. Upon receiving control signals, output signals are generated to drive the display panel. The multi-point driving circuit scheme can be fully or partially applied in the driver structure as required. In addition, a plurality of enable signals can be further adopted to activate each LED driving circuit, for avoiding the FIFO register used in the prior arts. By employing the disclosed technical contents, the present invention is effective in reducing both redundant power waste and circuit layout area of a conventional LED driver.

Abstract: A warp scheduling method includes: storing multiple first warps issued to a streaming multiprocessor in an instruction buffer module; marking multiple second warps which are able to be scheduled in the first warps by a schedulable warp indication window, wherein the number of the marked second warps is the size of the schedulable warp indication window; sampling a load/store unit stall cycle in each time interval to obtain a load/store unit stall cycle proportion; comparing the load/store unit stall cycle proportion with a stall cycle threshold value, and adjusting the size of the schedulable warp indication window and determining the second warps according to the comparison result; and issuing the second warps from the instruction buffer module to a processing module for execution.

Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.

Abstract: The present invention is related to a display device, including: a display panel having a plurality of sub-pixel areas, each including a pixel circuit, each pixel circuit including: a diode, configured to be in a forward-biasing state during a display phase of the pixel circuit for light-emitting and configured to be in a reverse-biasing state in a sensing phase of the pixel circuit to generate a sensing voltage; a driving transistor for driving the diode during the display phase; a readout transistor, with a gate receiving the sensing voltage during the sensing phase to serve as a source follower; first to seventh transistors, gate control signals applied to the gates of the first to seventh transistors respectively so that the pixel circuit switching between the display phase and the sensing phase; and a capacitor for storing a data voltage to be written to the diode in the display phase.

Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.

Abstract: The present invention relates to an image sensing device comprising: an image sensing array and an image processing circuit. The image sensing array includes sensing units, and the sensing units respectively generate multiple pieces of pixel data. The multiple pieces of pixel data are generated according to different frame rates under different exposure periods, and include a first pixel data of a first subframe and a second pixel data of a second subframe. The first pixel data is generated by exposing a first exposure period for a first frame rate, and the second pixel data is generated by exposing a second exposure period for a second frame rate. The first frame rate is less than the second frame rate. The first exposure period is greater than the second exposure period, and multiple pieces of the second pixel data are generated during one image capturing operation.

Abstract: The present invention relates to an image sensing structure, including: a sensing circuit, a storage circuit and a processing circuit. The sensing circuit is used to generate multiple sensing signals in different periods; the storage circuit is used to store the sensing signals. The storage circuit sequentially outputs a first sensing signal of a target object in a first period and a second sensing signal of the target object in a second period to the processing circuit. The processing circuit performs dynamic event detection processing through the first sensing signal and the second sensing signal. Also, the present invention relates to an image sensing device including the image sensing structure.

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.

Abstract: An image sensor and an operating method thereof are provided. The image sensor includes a first pixel circuit, a first column readout circuit, and a second column readout circuit. The first pixel circuit includes a first pixel unit, a first transfer transistor, a first reset transistor, a first readout transistor, and a first capacitor. The first column readout circuit includes a first circuit node. The second column readout circuit includes a bias transistor. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to the first circuit node, and a second terminal of the first readout transistor is coupled to the bias transistor.

Abstract: The disclosure provides a data receiver, including a first capacitor, a second capacitor, a first inverter and a second inverter. The first capacitor has a first terminal and a second terminal, and the first terminal receives a first input signal. The second capacitor has a third terminal and a fourth terminal, and the third terminal receives a second input signal. The first inverter has a first input terminal and a first output terminal. The second inverter has a second input terminal and a second output terminal. The first input terminal and the second output terminal are coupled to the second terminal of the first capacitor, and the second input terminal and the first output terminal are coupled to the fourth terminal of the second capacitor. The first output terminal generates a first output signal with a first output voltage, and the second output terminal generates a second output signal with a second output voltage.

Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.

Abstract: A display control system includes a plurality of driver circuits connected in series. A driver circuit among the plurality of driver circuits includes a receiver, a duty cycle correction circuit and a transmitter. The receiver is configured to receive a first signal from a previous driver circuit among the plurality of driver circuits. The duty cycle correction circuit, coupled to the receiver, is configured to adjust a duty cycle of the first signal to generate a second signal. The transmitter, coupled to the duty cycle correction circuit, is configured to transmit the second signal to a next driver circuit among the plurality of driver circuits.

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.