Abstract: A gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. The gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. The semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. The tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. The gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. An end portion of the chuck vacuum line may be provided through the outlet port.

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: A non-membrane deionization and ion-concentrating apparatus is connected to a power supply and includes a microfluidic channel, two current collectors and an electroactive material. The microfluidic channel is disposed between the two current collectors, and the power supply applies a voltage to the two current collectors. The electroactive material is coated and connected to at least one of the two current collectors, wherein the electroactive material has a reversible redox ability.

Abstract: A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

Abstract: The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Abstract: The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Abstract: The invention proposes a semiconductor device package structure, comprising a substrate, an adhesive layer and a die. The substrate has electrical through-holes to inter-connect a first and second wiring circuit on a top surface and a bottom surface of the substrate respectively, wherein a contact conductive bump is formed on the first wiring circuit. The under-fill adhesive layer is formed on the top surface and the first wiring circuit of the substrate except the area of the die. The die has a bump structure on the bonding pads of the die, wherein the bump structure of the die is electrically connected to the contact conductive bump of the first wiring circuit of the substrate.

Abstract: A method of LED package includes: forming a P-type through-hole and a N-type through-hole through a substrate; forming a conductive material on the sidewall of said P-type through-hole and N-type through-hole; forming a reflective layer on an upper surface of said substrate; aligning a P-type pad and a N-type pad with said P-type through-hole and said N-type through-hole, respectively, said P-type pad and N-type pad being formed on a first surface of a LED die, wherein said LED die is formed on said upper surface of said substrate; forming electrical connection from said P-type pad and said N-type pad by a copper refilling material within said P-type through-hole and said N-type through-hole; and a P-type terminal pad which positioned under said substrate electrically coupled to said P-type pad via said copper refilling material within said P-type through-hole, and a N-type terminal pad which positioned under said substrate electrically coupled to said N-type pad via said copper refilling material within said

Abstract: A method of LED package includes: forming a P-type through-hole and a N-type through-hole through a substrate; forming a conductive material on the sidewall of said P-type through-hole and N-type through-hole; forming a reflective layer on an upper surface of said substrate; aligning a P-type pad and a N-type pad with said P-type through-hole and said N-type through-hole, respectively, said P-type pad and N-type pad being formed on a first surface of a LED die, wherein said LED die is formed on said upper surface of said substrate; forming electrical connection from said P-type pad and said N-type pad by a copper refilling material within said P-type through-hole and said N-type through-hole; and a P-type terminal pad which positioned under said substrate electrically coupled to said P-type pad via said copper refilling material within said P-type through-hole, and a N-type terminal pad which positioned under said substrate electrically coupled to said N-type pad via said copper refilling material within said

Abstract: LED package includes a substrate with pre-formed P-type through-hole and N-type through-hole through said substrate, wherein a conductive material formed on the sidewall of said P-type through-hole and N-type through-hole; a reflective layer formed on an upper surface of said substrate; a LED die having P-type pad and N-type pad aligned with said P-type through-hole and said N-type through-hole; said P-type pad and N-type pad being formed on a first surface of said LED die; wherein said LED die is formed on said upper surface of said substrate; a copper refilling material within said P-type through-hole and said N-type through-hole thereby forming electrical connection from said P-type pad and said N-type pad; and a P-type terminal pad under said substrate and electrical coupled to said P-type pad through said copper refilling material within said P-type through-hole, a N-type terminal pad under said substrate and electrical coupled to said N-type pad through said copper refilling material within said N-type

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.