Abstract: A semiconductor structure includes a first semiconductor structure having a first conductivity type, a second semiconductor structure having a second conductivity type, an active structure disposed between the first semiconductor structure and the second semiconductor structure, a stress release structure disposed between the first semiconductor structure and the active structure, and an indium-containing layer disposed between the stress release structure and the first semiconductor structure. An indium content of the indium-containing layer is greater than an indium content of the stress release structure.

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

Abstract: A light-emitting device includes a first nitride semiconductor structure; a stress relief structure on the first nitride semiconductor structure including a plurality of narrow band gap layers and a plurality of wide band gap layers alternately stacked, wherein one of the plurality of wide band gap layers includes a plurality of wide band gap sub-layers and one of the plurality of wide band gap sub-layers includes aluminum; an active structure on the stress relief structure including a plurality of quantum well layers and a plurality of barrier layers alternately stacked, wherein one of the plurality of barrier layers includes a plurality of barrier sub-layers and one of the plurality of barrier sub-layers includes aluminum, an aluminum composition of the wide band gap sub-layer is greater than or equal to that of the barrier sub-layer, and an average aluminum composition of the wide band gap layer is greater than that of the barrier layer; and an electron blocking structure on the active structure.

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.