Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.

Abstract: A low-density parity-check (LDPC) code decoding method for decoding a set of initial log likelihood ratio (LLR) outputted by a de-mapping circuit. The decoding method comprises: receiving and storing the set of initial LLR from the de-mapping circuit; receiving and storing the set of initial LLR from a first buffer; receiving the set of initial LLR from a second buffer; performing a decoding operation according to the set of initial LLR to generate a set of intermediate LLR; determining whether the set of intermediate LLR is converged; when the set of intermediate LLR is not converged, storing the set of intermediate LLR back into the second buffer, wherein a storage space of the second buffer is greater than that of the first buffer; and when the set of intermediate LLR is converged, outputting the set of intermediate LLR as a set of decoded LLR.

Abstract: A decoding method for quasi-cyclic low-density parity-check codes is applied to a check matrix and multiple sets of transmission data. The check matrix includes N sub-matrices. The decoding method uses w (w<360) decoding units to perform decoding, and includes steps of: sending w sets of transmission data corresponding to a first block of a first sub-matrix to the w decoding units for decoding; and after completely decoding the w sets of transmission data corresponding to the first block of the first sub-matrix, sending w sets corresponding to a first block of a second sub-matrix to the w decoding units for decoding.

Abstract: A decoding method for a convolutionally coded signal is provided. The convolutionally coded signal includes a trellis. The decoding method includes determining a plurality of first sub-trellises from the trellis, decoding the first sub-trellises, determining a plurality of second sub-trellises from the trellis, boundaries of the second sub-trellises being different from boundaries of the first sub-trellises, and decoding the second sub-trellises.

Abstract: A decoding method for a convolutional code decoding device in a communication system includes receiving convolutional code data, determining the number of times of iteration, and performing an iterative decoding process for the number of times of iteration to decode the convolutional code data.

Abstract: A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

Abstract: A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

Abstract: An estimating method for estimating a phase difference of two frames is provided. The estimating method includes: providing a first sequence according to a header of a first frame; providing a second sequence according to a header of a second frame, wherein the first and second frames are successive frames, and the first and second sequences are pseudo noise sequences; performing a correlation calculation according to the first and second sequences to generate a plurality of correlation values; and estimating the phase difference between the first and second frames according to the correlation values.

Abstract: A decoding module for a communication device includes a first calculation circuit, outputting the larger between a first parameter and a second parameter as a first output parameter; a first arithmetic circuit, calculating a first product of a third parameter and a first slope, and a first difference between a first constant and the first product; a second arithmetic circuit, calculating a second product of the third parameter and a second slope, and a second difference between a second constant and the second product; a second calculation circuit, selecting the largest among a third constant, the first difference and the second difference and generating a second output parameter, wherein the third constant is zero; and an addition circuit, adding the first output parameter and the second output parameter to generate output information, according to which the communication device determines a data bit.

Abstract: A decoding method applied to a convolutionally coded signal is provided. The method includes: adjusting first input information according to a first scaling factor to generate first a-priori information; b) decoding the convolutionally coded signal according to systematic information and the first a-priori information to generate first extrinsic information; c) adjusting second input information according to a second scaling factor to generate second a-priori information, wherein the second scaling factor is generated according to the first extrinsic information and the first a-priori information; and d) decoding the convolutionally coded signal according to the systematic information and the second a-priori information to generate second extrinsic information. One of step (b) and step (d) further generates a-posteriori information as a decoding result.

Abstract: A decoding method applied to a convolutionally coded signal is provided. The method includes: adjusting first input information according to a first scaling factor to generate first a-priori information; b) decoding the convolutionally coded signal according to systematic information and the first a-priori information to generate first extrinsic information; c) adjusting second input information according to a second scaling factor to generate second a-priori information, wherein the second scaling factor is generated according to the first extrinsic information and the first a-priori information; and d) decoding the convolutionally coded signal according to the systematic information and the second a-priori information to generate second extrinsic information. One of step (b) and step (d) further generates a-posteriori information as a decoding result.

Abstract: An error correction apparatus for a digital signal received by a signal reception terminal includes two error correction modules. The first error correction module performs first error correction on an input signal to generate an intermediate signal satisfying a termination condition. The second error correction module receives and selectively performs second error correction on the intermediate signal to generate a corrected signal. The termination condition is associated with a maximum error correction capability of the second error correction.

Abstract: An estimating method for estimating a phase difference of two frames is provided. The estimating method includes: providing a first sequence according to a header of a first frame; providing a second sequence according to a header of a second frame, wherein the first and second frames are successive frames, and the first and second sequences are pseudo noise sequences; performing a correlation calculation according to the first and second sequences to generate a plurality of correlation values; and estimating the phase difference between the first and second frames according to the correlation values.

Abstract: A decoding method for a convolutionally coded signal is provided. The convolutionally coded signal includes a trellis. The decoding method includes determining a plurality of first sub-trellises from the trellis, decoding the first sub-trellises, determining a plurality of second sub-trellises from the trellis, boundaries of the second sub-trellises being different from boundaries of the first sub-trellises, and decoding the second sub-trellises.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.

Abstract: An error correction apparatus for a digital signal received by a signal reception terminal includes two error correction modules. The first error correction module performs first error correction on an input signal to generate an intermediate signal satisfying a termination condition. The second error correction module receives and selectively performs second error correction on the intermediate signal to generate a corrected signal. The termination condition is associated with a maximum error correction capability of the second error correction.

Abstract: A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

Abstract: A signal selection apparatus for selecting a target signal from a plurality of input signals is provided. The input signals correspond to different time indexes. The signal selection apparatus comprises a weight calculation unit for generating a corresponding weight respectively for each of the input signals, a processing unit for processing the input signals respectively to generate a plurality of processed signals according to the weights, and a selection unit for selecting a signal with a larger energy from the processed signals as the target signal, wherein the weights are used for adjusting an individual energy of the input signals such that the time index of the target signal is earlier within the input signals.

Abstract: A decoding method for determining a preferred survivor path in a decoding process is provided. The method includes calculating a first determination value of a first survivor path at a first time point, the first determination value being determined by a first sub determination value and a second determination value at a second time point, and the second time point being prior to the first time point; calculating a third determination value of a second survivor path at the first time point, the third determination value being determined by a second sub determination value and a fourth determination value at the second time point; and when a difference between the first determination value and the third determination value is equal to or less than a predetermined value, determining the preferred survivor path at the first time point according to the second and the fourth determination values, or the first and the second sub determination values.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.