Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.

Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: A power-saving data scheduling system includes a period decision module for selecting a cycle having a shortest delay time as a discontinuous reception (DRX) cycle for each user from quality of service (QoS) requirements related to network services and channel conditions, and a start offset decision module for calculating the number of users in each of periods of the DRX cycle. In addition, a DRX-aware scheduling module is provided for extending the on period by increasing priority of the user and resetting an inactivity timer if a period required by the user's load is shorter than an off period. Optimal DRX parameters and DRX-aware scheduling are used to resolve the existing issues that the channel conditions, system load and QoS are not taken into consideration when the DRX parameters are determined. Moreover, a power-saving data scheduling method is also provided.

Abstract: A power-saving data scheduling system for LTE and a method thereof are provided. The power-saving data scheduling system includes a period decision module for selecting a cycle having a shortest delay time as a discontinuous reception (DRX) cycle for each of user from quality of service (QoS) requirements related to network services and channel conditions, and a start offset decision module for calculating the number of users in each of periods of the DRX cycle. In addition, a DRX-aware scheduling module is provided for extending the on period by increasing priority of the user and resetting an inactivity timer if a period required by the user's load is shorter than an off period. Optimal DRX parameters and DRX-aware scheduling are used to resolve the existing issues that the channel conditions, system load and QoS are not taken into consideration when the DRX parameters are determined.