Patents by Inventor Yu-Hsin Lee

Yu-Hsin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250054810
    Abstract: A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and including a conductive interconnect; and a cap layer disposed on the interconnect structure. The cap layer includes a cap portion disposed on the conductive interconnect. The cap portion includes a plurality of two-dimensional material sheets stacked on each other and has a lower surface proximate to the conductive interconnect. The lower surface of the cap portion is formed with a plurality of dangling bonds such that the cap portion is adhered to the conductive interconnect through the dangling bonds.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wei LI, Hans HSU, Chien-Hsin HO, Yu-Chen CHAN, Blanka MAGYARI-KOPE, Shin-Yi YANG, Ming-Han LEE
  • Patent number: 12212325
    Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: January 28, 2025
    Assignee: MEDIATEK INC.
    Inventors: Fong-Wen Lee, Wen-Chieh Wang, Yu-Hsin Lin
  • Publication number: 20250017907
    Abstract: The present disclosure provides a method for preventing and/or treating liver fibrosis by using 6-methoxybenzoxazolinone and a Coix lachryma-jobi L. extract including 6-methoxybenzoxazolinone. The 6-methoxybenzoxazolinone and the Coix lachryma-jobi L. extract including 6-methoxybenzoxazolinone of the present disclosure achieve the effect of preventing and/or treating liver fibrosis through various efficacy experiments.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Inventors: Yu-Hsin Chen, Cheng Huang, Ching-Kuo Lee, Yu-Lin Cai
  • Patent number: 10498222
    Abstract: A power supply includes a rectifying circuit, a power converting circuit, and a snubber circuit. The rectifying circuit is configured to convert an ac input voltage to a first dc voltage. The power converting circuit is electrically coupled to the rectifying circuit at a node. The power converting circuit includes a switching element and is configured to convert the first dc voltage to a second dc voltage by selectively turning on or off the switching element. The snubber circuit is electrically coupled to the rectifying circuit and the power converting circuit at the node. When the first dc voltage is higher than a limiting level, the snubber circuit is configured to absorb the electricity power to prevent the voltage across the switching element from exceeding a safety upper limit.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 3, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Chieh Ou, Wei-Chieh Chao, Yu-Hsin Lee, Chi-You Ko
  • Publication number: 20190020264
    Abstract: A power supply includes a rectifying circuit, a power converting circuit, and a snubber circuit. The rectifying circuit is configured to convert an ac input voltage to a first dc voltage. The power converting circuit is electrically coupled to the rectifying circuit at a node. The power converting circuit includes a switching element and is configured to convert the first dc voltage to a second dc voltage by selectively turning on or off the switching element. The snubber circuit is electrically coupled to the rectifying circuit and the power converting circuit at the node. When the first dc voltage is higher than a limiting level, the snubber circuit is configured to absorb the electricity power to prevent the voltage across the switching element from exceeding a safety upper limit.
    Type: Application
    Filed: November 14, 2017
    Publication date: January 17, 2019
    Inventors: Cheng-Chieh OU, Wei-Chieh CHAO, Yu-Hsin LEE, Chi-You KO
  • Patent number: 7911056
    Abstract: A substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure includes a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the first surface. The trace layer has a plurality of traces, and at least one trace electrically connects to the ball pad. The solder mask has at least one opening corresponding to the ball pad. The size of the opening is larger than that of the ball pad. The solder mask covers the trace connecting to the ball pad. The problem of non-alignment of the solder ball can thus be solved, and the hole in the solder ball can be prevented when the substrate structure is welded with a PCB so that the reliability of solder ball welding can be improved.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: March 22, 2011
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Pai-Chou Liu, Yu-Hsin Lee
  • Patent number: 7662709
    Abstract: An improved surface mounting method applied in a semiconductor package process is provided, wherein the method comprises the following steps: First a substrate having at least one pad set on one surface of the substrate is provided. Then a mask having at least one opening associated with one of the at least one pad is set on the substrate, wherein each opening is separated into a plurality of sub-openings by a segregator to expose the pad. Subsequently, a printing process is conducted to form a conductive layer on each pad. After removing the mask, a passive device is set on the conductive layer over the pad, and a heating treatment is conducted to fix the passive device on the pad.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: February 16, 2010
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventors: Pai-Chou Liu, Wen-Shin Lin, Sheng-Hong Cheng, Yu-Hsin Lee, Ming-Chia Hsieh, Kuan-Hung Yeh, Chia-Wei Chang, Tsung-Chi Chen
  • Publication number: 20080042278
    Abstract: The present invention relates to a substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure comprises a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the first surface. The trace layer has a plurality of traces, and at least one trace electrically connects to the ball pad. The solder mask has at least one opening corresponding the ball pad. The size of the opening is larger than that of the ball pad. The solder mask covers the trace connecting to the ball pad. By utilizing the substrate structure of the invention, the problem of non-alignment of the solder ball can be solved, and the hole in the solder ball can be prevented when the substrate structure is welded with a PCB so that the reliability of solder ball welding can be improved.
    Type: Application
    Filed: January 10, 2007
    Publication date: February 21, 2008
    Inventors: Pai-Chou Liu, Yu-Hsin Lee
  • Publication number: 20070254469
    Abstract: An improved surface mounting method applied in a semiconductor package process is provided, wherein the method comprises the following steps: First a substrate having at least one pad set on one surface of the substrate is provided. Then a mask having at least one opening associated with one of the at least one pad is set on the substrate, wherein each opening is separated into a plurality of sub-openings by a segregator to expose the pad. Subsequently, a printing process is conducted to form a conductive layer on each pad. After removing the mask, a passive device is set on the conductive layer over the pad, and a heating treatment is conducted to fix the passive device on the pad.
    Type: Application
    Filed: December 28, 2006
    Publication date: November 1, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Pai-Chou Liu, Wen-Shin Lin, Sheng-Hong Cheng, Yu-Hsin Lee, Ming-Chia Hsieh, Kuan-Hung Yeh, Chia-Wei Chang, Tsung-Chi Chen