Patents by Inventor Yu-Hsing CHIANG

Yu-Hsing CHIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136472
    Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Chao-Hsing CHEN, Jia-Kuen WANG, Tzu-Yao TSENG, Tsung-Hsun CHIANG, Bo-Jiun HU, Wen-Hung CHUANG, Yu-Ling LIN
  • Publication number: 20140010276
    Abstract: A clock data recovery circuit includes an equalizer, a multi-phase clock generator, a sampling and check unit, a signal edge detection unit and an adjusting unit. The equalizer performs an equalization on an incoming data signal. The multi-phase clock generator generates multiple clock signals and at least one pair of check signals. The sampling and check unit samples the incoming data signal according to the clock signals to obtain a sequence, and checks whether the sequence matches a predetermined pattern. If so, the signal edge detection unit controls the sampling and check unit to detect a transition between values of the sequence two on two based on the pair of check signals to obtain a detection value. The adjusting unit determines whether the transition is too early or too late according to the detection value, and adjusts the equalization on the incoming data signal according to the determination result.
    Type: Application
    Filed: July 5, 2013
    Publication date: January 9, 2014
    Inventors: Chia-Hao HSU, Yu-Hsing CHIANG