Patents by Inventor Yu-Hsing Liang

Yu-Hsing Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11605652
    Abstract: An array substrate includes a substrate as well as a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a conductive structure sequentially formed thereon. The first insulating layer has a first opening communicated with a through hole of the substrate. The first conductive layer includes a first ring pattern extending from top of the first insulating layer into the first opening. The second insulating layer has a second opening communicated with the first opening. The second conductive layer includes a second ring pattern extending from top of the second insulating layer into the second opening. The first ring pattern laterally protrudes toward an axis of the through hole from the second ring pattern. The conductive structure extends from above the second insulating layer to a bottom surface of the substrate through the first and second openings and the through hole.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: March 14, 2023
    Assignee: Au Optronics Corporation
    Inventors: Yu-Hsing Liang, Hsiu-Hua Wang, Chan-Jui Liu, Pin-Miao Liu, Chun-Cheng Cheng
  • Publication number: 20200373333
    Abstract: An array substrate includes a substrate as well as a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a conductive structure sequentially formed thereon. The first insulating layer has a first opening communicated with a through hole of the substrate. The first conductive layer includes a first ring pattern extending from top of the first insulating layer into the first opening. The second insulating layer has a second opening communicated with the first opening. The second conductive layer includes a second ring pattern extending from top of the second insulating layer into the second opening. The first ring pattern laterally protrudes toward an axis of the through hole from the second ring pattern. The conductive structure extends from above the second insulating layer to a bottom surface of the substrate through the first and second openings and the through hole.
    Type: Application
    Filed: December 25, 2019
    Publication date: November 26, 2020
    Applicant: Au Optronics Corporation
    Inventors: Yu-Hsing Liang, Hsiu-Hua Wang, Chan-Jui Liu, Pin-Miao Liu, Chun-Cheng Cheng
  • Patent number: 10475826
    Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, a gate dielectric layer, a first dielectric layer, a source electrode, and a drain electrode. The gate electrode is disposed on a substrate. The semiconductor layer is disposed on the substrate and overlaps with the gate electrode. The gate dielectric layer is disposed between the gate electrode and the semiconductor layer. The first dielectric layer is disposed on the substrate and covers two sides of the gate electrode or the semiconductor layer. The dielectric constant of the first dielectric layer is less than the dielectric constant of the gate dielectric layer, and the dielectric constant of the first dielectric layer is less than 4. The source electrode and the drain electrode are disposed on the substrate. The source electrode is separated from the drain electrode, and the source electrode and the drain electrode separately contact the semiconductor layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 12, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Shuo-Yang Sun, Yu-Hsing Liang, Wan-Chen Huang, Chun-Cheng Cheng
  • Publication number: 20180331130
    Abstract: A thin film transistor includes a gate electrode, a semiconductor layer, a gate dielectric layer, a first dielectric layer, a source electrode, and a drain electrode. The gate electrode is disposed on a substrate. The semiconductor layer is disposed on the substrate and overlaps with the gate electrode. The gate dielectric layer is disposed between the gate electrode and the semiconductor layer. The first dielectric layer is disposed on the substrate and covers two sides of the gate electrode or the semiconductor layer. The dielectric constant of the first dielectric layer is less than the dielectric constant of the gate dielectric layer, and the dielectric constant of the first dielectric layer is less than 4. The source electrode and the drain electrode are disposed on the substrate. The source electrode is separated from the drain electrode, and the source electrode and the drain electrode separately contact the semiconductor layer.
    Type: Application
    Filed: May 4, 2018
    Publication date: November 15, 2018
    Inventors: Shuo-Yang SUN, Yu-Hsing LIANG, Wan-Chen HUANG, Chun-Cheng CHENG
  • Patent number: 8669558
    Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: March 11, 2014
    Assignee: AU Optronics Corp.
    Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang
  • Publication number: 20120292622
    Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.
    Type: Application
    Filed: January 12, 2012
    Publication date: November 22, 2012
    Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang