Patents by Inventor Yu-Hsiung Wang
Yu-Hsiung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120317Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.Type: ApplicationFiled: July 13, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
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Publication number: 20240055371Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.Type: ApplicationFiled: January 9, 2023Publication date: February 15, 2024Inventors: Der-Chyang Yeh, Kuo-Chiang Ting, Yu-Hsiung Wang, Chao-Wen Shih, Sung-Feng Yeh, Ta Hao Sung, Cheng-Wei Huang, Yen-Ping Wang, Chang-Wen Huang, Sheng-Ta Lin, Li-Cheng Hu, Gao-Long Wu
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Patent number: 11832448Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.Type: GrantFiled: July 15, 2021Date of Patent: November 28, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Publication number: 20230260941Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.Type: ApplicationFiled: May 13, 2022Publication date: August 17, 2023Inventors: Chih-Chia Hu, Yu-Hsiung Wang, Ming-Fa Chen
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Publication number: 20220359552Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 11430799Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: September 30, 2019Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Publication number: 20210343738Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having sidewalls that define a recess within an upper surface of the semiconductor substrate. A plurality of upper electrode segments are arranged over the semiconductor substrate and are vertically separated from the upper surface of the semiconductor substrate by a first dielectric layer. A lower electrode segment is arranged directly between the sidewalls of the semiconductor substrate and directly between adjacent ones of the plurality of upper electrode segments. A second dielectric layer is arranged directly between the sidewalls of the semiconductor substrate and the lower electrode segment and also directly between the plurality of upper electrode segments and the lower electrode segment.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Patent number: 11088159Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.Type: GrantFiled: January 2, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Publication number: 20200373317Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 10741569Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Patent number: 10672778Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: GrantFiled: October 4, 2017Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
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Publication number: 20200144280Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes disposed over a substrate and a lower electrode disposed between the plurality of upper electrodes. A charge storage layer continuously extends from along a first side of the lower electrode to along a second side of the lower electrode opposing the first side. The charge storage layer separates the lower electrode from the plurality of upper electrodes and the substrate. A silicide is disposed over the lower electrode and the plurality of upper electrodes. The silicide has sidewalls that are laterally separated by a distance directly overlying a top of the charge storage layer.Type: ApplicationFiled: January 2, 2020Publication date: May 7, 2020Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Publication number: 20200027889Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Patent number: 10535676Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.Type: GrantFiled: May 16, 2019Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Publication number: 20190273091Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of upper electrodes separated from a semiconductor substrate by a first dielectric layer. A lower electrode is laterally disposed between the plurality of upper electrodes and between sidewalls of the semiconductor substrate. A second dielectric layer lines opposing sidewalls and a lower surface of the lower electrode. The second dielectric layer laterally separates the lower electrode from the plurality of upper electrodes and from the sidewalls of the semiconductor substrate.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Patent number: 10297608Abstract: The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.Type: GrantFiled: April 7, 2017Date of Patent: May 21, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Publication number: 20190006380Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.Type: ApplicationFiled: October 4, 2017Publication date: January 3, 2019Inventors: Chen-Chin LIU, Wei Cheng WU, Yi Hsien LU, Yu-Hsiung WANG, Juo-Li YANG
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Publication number: 20170213841Abstract: The present disclosure relates to an integrated chip having an inter-digitated capacitor, and an associated method of formation. In some embodiments, the integrated chip has a plurality of upper electrodes separated from a substrate by a first dielectric layer. A plurality of lower electrodes vertically extend from between the plurality of upper electrodes to locations embedded within the substrate. A charge trapping dielectric layer is arranged between the substrate and the plurality of lower electrodes and between the plurality of upper electrodes and the plurality of lower electrodes. The charge trapping dielectric layer has a plurality of discrete segments respectively lining opposing sidewalls and a lower surface of one of the plurality of lower electrodes.Type: ApplicationFiled: April 7, 2017Publication date: July 27, 2017Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Patent number: 9691780Abstract: The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer.Type: GrantFiled: September 25, 2015Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wan-Chen Chen, Yu-Hsiung Wang, Han-Yu Chen
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Patent number: 9679909Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.Type: GrantFiled: June 25, 2015Date of Patent: June 13, 2017Assignee: Taiwan Samiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Yu-Hsiung Wang, Chen-Chin Liu