Abstract: A method for collision warning implemented in an electronic device includes fusing obtained radar information and image information; recognizing at least one obstacle in a traveling direction of a vehicle according to the fused radar information and image information; determining motion parameters of the at least one obstacle and the vehicle according to the radar information and the image information; and calculating a collision time between the vehicle and the at least one obstacle according to the motion parameters, and issuing a collision warning.

Abstract: Methods and systems are presented for providing automated online chat assistance in an online chat session. One or more utterances transmitted from a user device of a user via the online chat session are obtained. The one or more utterances are provided to a first prediction model to predict an intent of a user. If it is determined that the first prediction model is unable to predict the intent of the user based on the one or more utterances, the one or more utterances are provided to a second prediction model. After predicting the intent of the user by the second prediction model, the intent is used by a chat robot to provide a dialogue with the user via the online chat session. The one or more utterances and the predicted intent are used to re-train the first prediction model.

Abstract: Methods and systems are presented for providing automated online chat assistance in an online chat session. One or more utterances transmitted from a user device of a user via the online chat session are obtained. The one or more utterances are provided to a first prediction model to predict an intent of a user. If it is determined that the first prediction model is unable to predict the intent of the user based on the one or more utterances, the one or more utterances are provided to a second prediction model. After predicting the intent of the user by the second prediction model, the intent is used by a chat robot to provide a dialogue with the user via the online chat session. The one or more utterances and the predicted intent are used to re-train the first prediction model.

Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.

Abstract: Methods and systems are presented for providing automated online chat assistance in an online chat session. One or more utterances transmitted from a user device of a user via the online chat session are obtained. The one or more utterances are provided to a first prediction model to predict an intent of a user. If it is determined that the first prediction model is unable to predict the intent of the user based on the one or more utterances, the one or more utterances are provided to a second prediction model. After predicting the intent of the user by the second prediction model, the intent is used by a chat robot to provide a dialogue with the user via the online chat session. The one or more utterances and the predicted intent are used to re-train the first prediction model.

Abstract: A method of forming a semiconductor structure includes depositing a mask layer over a substrate. The method includes etching the substrate to define a first opening. The method includes depositing a sacrificial material in the first opening. The method includes depositing a dielectric liner along sidewalls of the first opening, wherein a bottom surface of the dielectric liner contacts the sacrificial material. The method includes removing the sacrificial material. The method includes etching the substrate to enlarge the first opening to define a second opening. The second opening includes a first portion extending a first depth from the dielectric material in a first direction perpendicular to a top surface of the substrate, and a second portion extending in a second direction, parallel to the top surface of the substrate. The method includes removing the dielectric liner. The method includes filling the second opening with a dielectric material.

Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a second conductive type, a channel between source and drain, and a gate over the channel. The channel includes dopants of the first conductive type. The gate includes a work function setting layer of the second conductive type. The present disclosure also provides a method for manufacturing an FET with multi-threshold voltages scheme. The method includes exposing channels of a first transistor of a first conductive type and a first transistor of a second conductive type from a first mask, doping the channels with dopants of the first conductive type, exposing channels of a second transistor of the first conductive type and a second conductive type from a second mask, and doping the channels with dopants of the second conductive type.

Abstract: A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.

Abstract: Growth of SiGe on a significantly lattice mismatched substrate (e.g., Si) is provided by depositing a SiGe buffer layer at a growth temperature, then annealing the resulting structure at a temperature higher than the growth temperature. Additional buffer layers can be included following the same steps. The SiGe buffer is significantly lattice mismatched with respect to the substrate, and is preferably substantially lattice matched with a SiGe device to be grown on top of the buffer. The resulting buffer structure is relatively thin and provides low defect density, and low surface roughness. Disadvantages of thick graded buffer layers, such as high cost, high surface roughness, mechanical fragility, and CTE mismatch, are thereby avoided.

Abstract: Si—Ge quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1?xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. A preferred method of providing such quantum well structures on a substrate (e.g., a silicon substrate) is to grow a first Ge-rich Si—Ge buffer layer on the substrate, and then anneal the resulting layered structure. In many cases it is further preferred to grow a second Ge-rich Si—Ge buffer layer on top of the first buffer layer and anneal the resulting layered structure.

Abstract: SiGe quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. Optical modulators and/or detectors according to the invention are suitable for inclusion in waveguide-based optical interconnects. Such interconnects can be on-chip interconnects or chip to chip interconnects.

Abstract: SiGe quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. Optical modulators including such SiGe quantum wells can be operated at temperatures other than room temperature. Such temperature control is preferred for providing optical modulators that operate in the telecommunication C band (˜1530 nm to ˜1565 nm).

Abstract: SiGe quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. Optical modulators and/or detectors according to the invention are suitable for inclusion in waveguide-based optical interconnects. Such interconnects can be on-chip interconnects or chip to chip interconnects.

Abstract: SiGe quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. Embodiments of the invention having a surface parallel configuration are especially suitable for use in fiber coupled devices. Such surface parallel devices have light propagating in the plane of the quantum wells, in a device geometry that is preferably not single-mode waveguided.

Abstract: SiGe quantum wells where the well material has a lowest conduction band energy minimum at k=0 (the ? point of the first Brillouin zone) are provided. Quantum well structures that satisfy this condition have “Kane-like” bands at and near k=0 which can provide physical effects useful for various device applications, especially optical modulators. In the Si1-xGex material system, this condition on the band structure is satisfied for x greater than about 0.7. The quantum well barrier composition may or may not have Kane-like bands. Embodiments of the invention having a surface parallel configuration are especially suitable for use in fiber coupled devices. Such surface parallel devices have light propagating in the plane of the quantum wells, in a device geometry that is preferably not single-mode waveguided.

Abstract: Optical devices having integrated waveguide and active areas are realized using a crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a growth region is formed such that the region is isolated from a silicon portion of silicon material. The region extends from a silicon-based seeding area of the substrate. A semiconductor material is deposited on a Silicon-based seeding area and in the growth region. A single crystalline material is formed from the deposited semiconductor material by heating and cooling the deposited semiconductor material while directing growth of the semiconductor material from the Silicon-based seeding area and through an opening sufficiently narrow to mitigate crystalline defects. A light-communicating device is formed by etching the silicon material over an insulator layer and etching the single crystalline material.