Patents by Inventor Yu-Hsuan Tsai

Yu-Hsuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011501
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11008222
    Abstract: A metal bronze compound is provided. The metal bronze compound is a compound represented by formula (1) below. In formula (1), “A” represents at least one type of cation. “M” represents at least two types of ions selected from a transition metal and a metalloid. “x” represents the sum of the number of the at least one type of cation used as “A”. “y” represents the sum of the number of the at least two types of ions selected from the transition metal and the metalloid used as “M”. “z” represents the number of oxygen ion. The values of “x”, “y” and “z” balance the charge number of formula (1).
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 18, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Ming-Chih Tsai, Yu-Hsuan Ho
  • Patent number: 11004786
    Abstract: A package structure includes a die, a TIV, a first encapsulant, a RDL structure, a thermal dissipation structure and a second encapsulant. The die has a first surface and a second surface opposite to each other. The TIV is laterally aside the die. The first encapsulant encapsulates sidewalls of the die and sidewalls of the TIV. The RDL structure is disposed on the first surface of the die and on the first encapsulant, electrically connected to the die and the TIV. The thermal dissipation structure is disposed over the second surface of die and electrically connected to the die through the TIV and the RDL structure. The second encapsulant encapsulates sidewalls of the thermal dissipation structure.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11004758
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Publication number: 20210128776
    Abstract: A negative ion generator includes a fiber bundle, a boost circuit board, a sleeve component and an electrically conductive adhesive. The fiber bundle includes a combining portion. The boost circuit board is connected to the fiber bundle and includes an electrically conductive terminal. An output end of the electrically conductive terminal is inserted into the combining portion of the fiber bundle. The boost circuit board provides a high-voltage current to the fiber bundle to enable the fiber bundle to emit negative ions by corona discharging. An accommodating space is enclosed by the sleeve component. The combining portion of the fiber bundle is installed inside the accommodating space. The electrically conductive adhesive is poured into the accommodating space and located between the combining portion of the fiber bundle and the output end of the electrically conductive terminal for adhering and electrically connecting the fiber bundle to the electrically conductive terminal.
    Type: Application
    Filed: March 1, 2020
    Publication date: May 6, 2021
    Inventors: Hung-Hsuan Chien, Yu-Fan Tsai
  • Patent number: 10991595
    Abstract: A dry etching process for manufacturing a trench structure of a semiconductor apparatus, including the steps of: step 1, providing a semiconductor substrate, wherein the semiconductor substrate is provided with a patterned photoresist layer and placed in a reaction chamber; step 2, introducing a first etching gas into the reaction chamber to perform a first etching process to form a trench, wherein the first etching gas includes sulfur hexafluoride, oxygen, helium, nitrogen trifluoride, and a first organic silicide; step 3, introducing a second etching gas into the reaction chamber to perform a second etching process to further etch the trench, wherein the second etching gas includes sulfur hexafluoride, oxygen, helium, and a second organic silicide; and step 4, introducing a third etching gas into the reaction chamber to perform a third etching process, wherein the third etching gas includes hydrobromic acid, oxygen, and helium.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN CARBON NANO TECHNOLOGY CORPORATION
    Inventors: Kuang-Jui Chang, Yu-Hsuan Liao, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Patent number: 10841679
    Abstract: A microelectromechanical systems package structure includes a first substrate, a transducer unit, a semiconductor chip and a second substrate. The first substrate defines a through hole. The transducer unit is electrically connected to the first substrate, and includes a base and a membrane. The membrane is located between the through hole and the base. The semiconductor chip is electrically connected to the first substrate and the transducer unit. The second substrate is attached to the first substrate and defines a cavity. The transducer unit and the chip are disposed in the cavity, and the second substrate is electrically connected to the transducer unit and the semiconductor chip through the first substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Liang Hsiao, Yu-Hsuan Tsai, Pu Shan Huang, Ching-Han Huang, Lu-Ming Lai
  • Patent number: 10804413
    Abstract: A package component includes a base layer, a sensing layer, a photo-curable adhesive, a cover layer and a first filter structure. The photo-curable adhesive and the sensing layer are disposed on the base layer. The sensing layer includes a sensing unit surrounded by the photo-curable adhesive. The cover layer is disposed on the sensing layer. The first filter structure faces the photo-curable adhesive and is disposed on the cover layer. The first filter structure is configured for transmitting a curing light which is used to cure the photo-curable adhesive, and for reflecting a detectable light which is to be sensed by the sensing unit, where the wavelength of the curing light is different from the wavelength of the detectable light.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 13, 2020
    Assignee: KINGPAK TECHNOLOGY INC
    Inventor: Yu-Hsuan Tsai
  • Publication number: 20200283288
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming Yen LEE, Chia-Hao SUNG, Ching-Han HUANG, Yu-Hsuan TSAI
  • Patent number: 10734337
    Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 4, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu
  • Patent number: 10720751
    Abstract: An optical package structure includes a substrate having a first surface, an interposer bonded to the first surface through a bonding layer, the interposer having a first area from a top view perspective, and an optical device on the interposer, having a second area from the top view perspective, the first area being greater than the second area. A method for manufacturing the optical package structure is also provided.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 21, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Hsuan Tsai, Lu-Ming Lai, Ying-Chung Chen, Shih-Chieh Tang
  • Publication number: 20200206735
    Abstract: A detection method for enhancing detection signal intensity is provided. The detection method includes the following steps. Firstly, a detection device is provided. The detection device includes a channel, an inlet port and an air chamber. The air chamber includes an elastic layer. A bonding material is immobilized in the channel and served as a reaction area. Then, a sample containing a detection material is loaded into the inlet port. As the elastic layer is moved upwardly and downwardly, the sample is moved toward the air chamber and the inlet port in a reciprocating manner. Consequently, the possibility of combining the detection material of the sample with the bonding material in the reaction area is increased. Afterwards, an optical signal from the reaction area is measured.
    Type: Application
    Filed: December 10, 2019
    Publication date: July 2, 2020
    Inventors: Chi-Han Chiou, Shu-Hsien Liao, Yu-Hsuan Tsai, Ching-Yu Chang
  • Patent number: 10689248
    Abstract: The present disclosure relates to a semiconductor device package. The semiconductor device package includes a substrate, a support structure, an electronic component and an adhesive. The support structure is disposed on the substrate. The electronic component is disposed on the support structure. The adhesive is disposed between the substrate and the electronic component and covers the support structure. A hardness of the support structure is less than a hardness of the electronic component.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Yen Lee, Chia Hao Sung, Ching-Han Huang, Yu-Hsuan Tsai
  • Publication number: 20200140262
    Abstract: A semiconductor device package includes a carrier; a sensor element disposed on or within the carrier; a cover disposed above the carrier and comprising a top surface, a bottom surface and an inner sidewall, the inner sidewall defining a penetrating hole extending from the top surface to the bottom surface; and a light transmissive element covering the penetrating hole, wherein the sensor element senses or detects light passing through the light transmissive element.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ching-Han HUANG, Hsun-Wei CHAN, Yu-Hsuan TSAI
  • Patent number: 10526200
    Abstract: A semiconductor device package includes: (1) a carrier; (2) a sensor element disposed on or within the carrier; and (3) a cover including a top surface, a bottom surface and an inner sidewall, the inner sidewall defining a penetrating hole extending from the top surface to the bottom surface, and the penetrating hole exposing the sensor element. The semiconductor device package is characterized such that (i) the inner sidewall is divided into an upper portion and a lower portion, the upper portion is substantially perpendicular to the top surface, and the lower portion is tilted; or (ii) the entire inner sidewall is tilted. The lower portion of the inner sidewall or the entire inner sidewall is tilted at an angle of between about 10° to less than about 90°, relative to the top surface.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: January 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ching-Han Huang, Hsun-Wei Chan, Yu-Hsuan Tsai
  • Publication number: 20200002162
    Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
    Type: Application
    Filed: June 25, 2019
    Publication date: January 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Yu-Hsuan TSAI, Yin-Hao CHEN, Hsin Lin WU, San-Kuei YU
  • Publication number: 20190267298
    Abstract: A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 29, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsin Lin WU, Yu-Hsuan TSAI, Chang Chin TSAI, Lu-Ming LAI, Ching-Han HUANG
  • Publication number: 20190198469
    Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
    Type: Application
    Filed: March 5, 2019
    Publication date: June 27, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Yu-Hsuan TSAI, Yu-Ying LEE, Sheng-Ming WANG, Wun-Jheng SYU
  • Publication number: 20190097387
    Abstract: An optical package structure includes a substrate having a first surface, an interposer bonded to the first surface through a bonding layer, the interposer having a first area from a top view perspective, and an optical device on the interposer, having a second area from the top view perspective, the first area being greater than the second area. A method for manufacturing the optical package structure is also provided.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Hsuan TSAI, Lu-Ming LAI, Ying-Chung CHEN, Shih-Chieh TANG
  • Patent number: 10224298
    Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: March 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Yu-Hsuan Tsai, Yu-Ying Lee, Sheng-Ming Wang, Wun-Jheng Syu