Abstract: A method of managing Universal Serial Bus (USB) data transmission and wireless communication of an electronic device is disclosed.

Abstract: Various patterning methods involved with manufacturing semiconductor devices are disclosed herein. A method for fabricating a semiconductor structure (for example, interconnects) includes forming a patterned photoresist layer over a dielectric layer. An opening (hole) is formed in the patterned photoresist layer. In some embodiments, a surrounding wall of the patterned photoresist layer defines the opening, where the surrounding wall has a generally peanut-shaped cross section. The opening in the patterned photoresist layer can be used to form an opening in the dielectric layer, which can be filled with conductive material. In some embodiments, a chemical layer is formed over the patterned photoresist layer to form a pair of spaced apart holes defined by the chemical layer, and an etching process is performed on the dielectric layer using the chemical layer as an etching mask to form a pair of spaced apart holes through the dielectric layer.

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract: A method of handling transmission for a host in a data transmission system includes establishing a connection with a device of the data transmission system via a first frequency; receiving a negotiating information from the device; and re-establishing the connection with the device via a second frequency when the negotiating information reveals that the second frequency is available for the host to communicate with the device; wherein the second frequency is different than the first frequency.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: A connection port module is mounted to a side wall of a housing of an electronic device. The electronic device includes a control circuit. The connection port module includes a rotating box, a circuit board, and at least one connection port. The rotating box is formed with at least one opening. The circuit board is electrically coupled to the control circuit. The connection port corresponds in number to the opening and is electrically coupled to the circuit board. The connection port is disposed correspondingly to the opening. The rotating box is pivotable relative to the housing between a first position and a second position.

Abstract: A USB host controller is provided. The USB host controller includes an endpoint management unit, a transfer management unit, and a schedule management unit. The endpoint management unit manages endpoint configurations of a USB device, wherein the USB device includes a plurality of endpoints and the endpoint configurations include a plurality of statuses of the endpoints of the USB device. The transfer management unit transfers data regarding transfer information of the endpoints of the USB device between a system memory and the USB host controller. The schedule management unit simultaneously manages packet transfer of at least two endpoints of the USB device.

Abstract: A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation.

Abstract: An active output buffer controller is used for controlling a packet data output of a main buffer in a network device. The active output buffer controller has a credit evaluation circuit and a control logic. The credit evaluation circuit estimates a credit value based on at least one of an ingress data reception status of the network device and an egress data transmission status of the network device. The control logic compares the credit value with a first predetermined threshold value to generate a comparison result, and controls the packet data output of the main buffer according to at least the comparison result.

Abstract: One packet output controller includes a scheduler and a dequeue device. The scheduler performs a single scheduler operation to schedule an output queue selected from a plurality of output queues associated with an egress port. The dequeue device dequeues multiple packets from the scheduled output queue decided by the single scheduler operation. Another packet output controller includes a scheduler and a dequeue device. The scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler performs a current scheduler operation, regardless of a status of a packet transmission of a scheduled output queue decided by a previous scheduler operation. The dequeue device dequeues at least one packet from the scheduled output queue decided by the current scheduler operation after the packet transmission of the scheduled output queue decided by the previous scheduler operation is complete.

Abstract: A wireless communications system co-located with an interface apparatus includes a radio subsystem. The radio subsystem includes a transmission circuit arranged for performing a radio transmission, and a reception circuit arranged for performing a radio reception when the interface apparatus operates in a first operational state. The interface apparatus operates in one of a plurality of operational states including the first operational state and a second operational state, and a power consumption of the interface apparatus in the first operational state is lower than a power consumption of the interface apparatus in the second operational state.

Abstract: A method of reducing mutual interference between Universal Serial Bus (USB) data transmission and wireless communication for an electronic device is disclosed. The method comprises establishing a plurality of physical layer links for the USB data transmission in a plurality of supported USB modes; dynamically selecting one of the supported USB modes according to the wireless communication; and performing the USB data transmission in the selected USB mode.

Abstract: A method of handling transmission for a host in a data transmission system includes establishing a connection with a device of the data transmission system via a first frequency; receiving a negotiating information from the device; and re-establishing the connection with the device via a second frequency when the negotiating information reveals that the second frequency is available for the host to communicate with the device; wherein the second frequency is different than the first frequency.

Abstract: A USB host controller is provided. The USB host controller includes an endpoint management unit, a transfer management unit, and a schedule management unit. The endpoint management unit manages endpoint configurations of a USB device, wherein the USB device includes a plurality of endpoints and the endpoint configurations include a plurality of statuses of the endpoints of the USB device. The transfer management unit transfers data regarding transfer information of the endpoints of the USB device between a system memory and the USB host controller. The schedule management unit simultaneously manages packet transfer of at least two endpoints of the USB device.

Abstract: Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.

Abstract: Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.