Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.

Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.