Patents by Inventor Yu Hua

Yu Hua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250035718
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen -Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20250040051
    Abstract: A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.
    Type: Application
    Filed: August 21, 2023
    Publication date: January 30, 2025
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Hung KUO, Kuo-Ching CHEN, Yu-Cheng HUANG, Yu-Hua CHEN
  • Patent number: 12211906
    Abstract: A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Tseng, Po-Wei Liu, Hung-Ling Shih, Tsung-Yu Yang, Tsung-Hua Yang, Yu-Chun Chang
  • Patent number: 12211801
    Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.
    Type: Grant
    Filed: June 19, 2023
    Date of Patent: January 28, 2025
    Assignee: Parabellum Strategic Opportunities Fund LLC
    Inventors: Yu-Hsiang Hu, Chen-Hua Yu, Hung-Jui Kuo
  • Patent number: 12211915
    Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: January 28, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
  • Publication number: 20250030588
    Abstract: Provided are a data modulation method and apparatus, a device, and a storage medium. The method includes: a modulation manner is configured, and data is modulated by using the modulation manner. That the constellation point modulation symbol of the modulation manner is formed by combining the first group of constellation point modulation symbols and the second group of constellation point modulation symbols includes: adjusting a phase of the second group of constellation point modulation symbols based on a phase of the first group of constellation point modulation symbols; and forming, based on a combination of the first group of and adjusted second group of constellation point modulation symbols, the constellation point modulation symbol of the modulation manner.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 23, 2025
    Applicant: ZTE CORPORATION
    Inventors: Yu XIN, Jian HUA, Liujun HU, Guanghui YU, Jin XU
  • Publication number: 20250031389
    Abstract: A capacitor device and a manufacturing method thereof are disclosed in the present invention. The capacitor device includes pad structures, bottom electrodes, a top electrode, and a dielectric layer. The bottom electrodes are disposed on the pad structures, respectively. The top electrode is disposed on the bottom electrodes. The dielectric layer is disposed between the top electrode and the bottom electrodes. The top electrode includes at least one void. The manufacturing throughput of the manufacturing method of the memory device may be enhanced accordingly.
    Type: Application
    Filed: November 13, 2023
    Publication date: January 23, 2025
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Bingxing Wu, Jung-Hua Chen, Wei-Ming Hsiao, Yu-Cheng Tung, Qiangwei Xu
  • Patent number: 12205860
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250022803
    Abstract: An electronic package is provided and includes a protection layer formed on the electronic structure having a plurality of conductors to cover the plurality of conductors, a dielectric layer having a plurality of grooves to enable the electronic structure to be bonded onto one side of the dielectric layer with the protection layer thereon such that each of the plurality of conductors is correspondingly accommodated in each of the plurality of grooves, and a plurality of conductive components disposed on another side of the dielectric layer. Accordingly, the design of the grooves is used to correspond to the high and low surfaces of the electronic structure such that the problem of poor manufacturing process can be avoided.
    Type: Application
    Filed: September 27, 2024
    Publication date: January 16, 2025
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: You-Chen LIN, Yu-Min LO, Kuo-Hua YU, Jun-Hao FENG
  • Publication number: 20240412390
    Abstract: A method for image alignment is provided. The method for image alignment includes the following stages. A first image with a first property from a first sensor is received. A second image with a second property from a second sensor is received. The first property is similar to the second property. The first feature correspondence between the first image and the second image is calculated. A third image with a third property from the first sensor and a fourth image with a fourth property from the second image sensor are received. The third property is different from the fourth property. Image alignment is performed on the third image and the fourth image based on the first feature correspondence between the first image and the second image.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Inventors: Yen-Yang CHOU, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Pin-Wei CHEN, Yu-Hua HUANG, Yun-I CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN
  • Publication number: 20240389232
    Abstract: A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 21, 2024
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Hung KUO, Kuo-Ching CHEN, Yu-Cheng HUANG, Yu-Hua CHEN
  • Publication number: 20240381533
    Abstract: A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.
    Type: Application
    Filed: June 2, 2023
    Publication date: November 14, 2024
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Hung KUO, Kuo-Ching CHEN, Yu-Cheng HUANG, Yu-Hua CHEN
  • Publication number: 20240354887
    Abstract: A graphics system is provided. The graphics system includes a frame buffer, a timing controller, and a processing unit. The processing unit generating an output video frame based on a raw video frame. The output video frame includes the main window and a picture-in-picture window overlaid on the main window, and the picture-in-picture window is generated by zooming in a target region of the main window. The timing controller is configured to generates a first vertical synchronization signals to control the input timing for the processing unit to write the raw video frame into the frame buffer, and generate a second vertical synchronization signal to control an output timing for the processing unit to read the raw video frame from the frame buffer and generating the output video frame, such that specific timing conditions are met.
    Type: Application
    Filed: April 17, 2024
    Publication date: October 24, 2024
    Inventors: Yu-Hua WU, Yong-Guan LIAO, Kuan-Yu CHEN
  • Publication number: 20240338804
    Abstract: A method for high dynamic range imaging is provided. The method includes the following stages. A first image from a first sensor capable of sensing a first spectrum is received. A second image from a second sensor capable of sensing a second spectrum is received. The second spectrum has a higher wavelength range as compared to the first spectrum. A first image feature from the first image and a second image feature from the second image are retrieved. The first and second images are fused by referencing the first image feature and the second image feature to generate a final image.
    Type: Application
    Filed: April 6, 2023
    Publication date: October 10, 2024
    Inventors: Pin-Wei CHEN, Keh-Tsong LI, Shao-Yang WANG, Chia-Hui KUO, Hung-Chih KO, Yun-I CHOU, Yu-Hua HUANG, Yen-Yang CHOU, Chien-Ho YU, Chi-Cheng JU, Ying-Jui CHEN
  • Publication number: 20240273675
    Abstract: An image calibration method is applied to an image calibration device includes an image receiver and an operation processor. The image calibration method of providing a motion deblur function includes driving a first camera to capture a first image having a first exposure time, driving a second camera disposed adjacent to the first camera to capture a second image having a second exposure time different from and at least partly overlapped with the first exposure time, and fusing a first feature of the first image and a second feature of the second image to generate a fusion image.
    Type: Application
    Filed: January 2, 2024
    Publication date: August 15, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Hua Huang, Pin-Wei Chen, Keh-Tsong Li, Shao-Yang Wang, Chia-Hui Kuo, Hung-Chih Ko, Yun-I Chou, Yen-Yang Chou, Chien-Ho Yu, Chi-Cheng Ju, Ying-Jui Chen
  • Publication number: 20240266985
    Abstract: A power integrated module (PIM) and a motor control system are provided. The PIM is adapted to drive a motor. The PIM includes a first transformation circuit, a second transformation circuit, and a plurality of shunt units. The first transformation circuit includes a plurality of first half-bridge circuits, and a coupling relationship among the first half-bridge circuits is selected, so that the first transformation circuit is operated in a rectifier mode or an inverter mode. The second transformation circuit includes a plurality of second half-bridge circuits coupled to the motor. The shunt units are respectively coupled between the second half-bridge circuits and the motor and configured to sense a current between the second transformation circuit and the motor.
    Type: Application
    Filed: April 26, 2023
    Publication date: August 8, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Shian-Chiau Chiou, Yu-Hua Cheng, Chih-Ming Tzeng
  • Patent number: 12053860
    Abstract: A constant torque tool provided, including: a driver body, including a handle and a working rod connected with the handle, at least one of the handle and the working rod being integrally formed with a first blocking structure; a sleeve member, being rotatably disposed around the driver body and integrally formed with a second blocking structure, the second blocking structure being releasably stuck with the first blocking structure in a rotation direction of the sleeve member; wherein when there is a relative torque greater than a predetermined torque between the sleeve member and the driver body, at least one of the second blocking structure and the first blocking structure deforms and the second blocking structure is slidable over the first blocking structure in the rotation direction.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: August 6, 2024
    Inventor: Yu-Hua Ou
  • Patent number: 12044475
    Abstract: A thermal pretreatment method for organic solid waste based on forced hot air convection is performed as follows. Experimental materials are grouped into an experimental group and a control group. The experimental group is subjected to thermal pretreatment in a thermal pretreatment device, and then removed. The experimental group and the control group are subjected to enzymatic hydrolysis and physicochemical characterization, and the analysis results are compared. A thermal pretreatment device for organic solid waste based on forced hot air convection is also provided.
    Type: Grant
    Filed: August 14, 2023
    Date of Patent: July 23, 2024
    Assignee: Tongji University
    Inventors: Yu Hua, Xiaohu Dai
  • Publication number: 20240186724
    Abstract: An antenna module includes an antenna box and a first connection wire. The antenna box can include a first antenna, a second antenna, a first connection terminal, a second connection terminal and a housing. The first and second antennas are located in the housing and the housing has a first opening collectively exposing a portion of the first connection terminal and a portion of the second connection terminal. Each of the first and second antennas is adapted to receive or transmit wireless signals according to one of a plurality of wireless communication standards and the first and second antennas are electrically connected to the first and second connection terminals, respectively. The wireless communication standards can be different from each other.
    Type: Application
    Filed: November 6, 2023
    Publication date: June 6, 2024
    Inventors: Tsai-Yi Yang, Yung-Sheng Tseng, Bo-Yuan Chang, Sheng-Shen Chang, Yu-Hua Chen, Shih-Shih Chien, En-Chin Wei
  • Publication number: 20240114116
    Abstract: A multi-projector system and a method of calibrating the multi-projector system are provided. The method includes: controlling a first projector to project a first image, and capturing and generating a first captured image including the first image to obtain a first color value from the first captured image through an image capturing device; projecting a second image according to a first projection parameter, and capturing and generating a second captured image including the second image to obtain a second color value from the second captured image through the image capturing device, wherein the first projection parameter includes an electrical parameter of a light source module of the second projector; calculating an absolute difference between the first color value and the second color value; and adjusting the first projection parameter to update the absolute difference in response to the absolute difference being greater than a first threshold.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Applicant: Coretronic Corporation
    Inventors: Xuan-En Fung, Chun-Lin Chien, Yu-Wen Lo, Yu-Hua Yang