Patents by Inventor Yu-Hua Chung
Yu-Hua Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11764166Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.Type: GrantFiled: March 30, 2021Date of Patent: September 19, 2023Assignees: Industrial Technology Research Institute, Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Wen Yang, Hsin-Cheng Lai, Chieh-Wei Feng, Tai-Jui Wang, Yu-Hua Chung, Tzu-Yang Ting
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Patent number: 11387230Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.Type: GrantFiled: November 8, 2018Date of Patent: July 12, 2022Assignee: Industrial Technology Research InstituteInventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Yu-Hua Chung
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Publication number: 20220005768Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.Type: ApplicationFiled: March 30, 2021Publication date: January 6, 2022Applicant: Industrial Technology Research InstituteInventors: Jui-Wen Yang, Hsin-Cheng Lai, Chieh-Wei Feng, Tai-Jui Wang, Yu-Hua Chung, Tzu-Yang Ting
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Patent number: 11088135Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.Type: GrantFiled: May 8, 2019Date of Patent: August 10, 2021Assignee: Industrial Technology Research InstituteInventors: Yu-Hua Chung, Tai-Jui Wang, Chieh-Wei Feng
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Patent number: 10941498Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.Type: GrantFiled: June 20, 2019Date of Patent: March 9, 2021Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Hsun Chu, Chien-Chou Tseng, Ming-Huan Yang, Tai-Jui Wang, Yu-Hua Chung, Chieh-Wei Feng
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Patent number: 10786719Abstract: A swimming posture correction method and a swimming posture correction system, adapted for a computing apparatus to correct a swimming posture of a swimmer using at least two gravity sensors, are provided. The gravity sensors are respectively disposed at ends of at least two limbs of the swimmer performing a relative stroke action. In the method, body parameters of the swimmer are obtained and a reference index of coordination for implementing a swimming posture suitable for the body parameters is captured. A stroke of the limb is monitored using the gravity sensors to obtain a timing diagram of the limbs performing a stroke promotion action. Then, an index of coordination of the swimmer is calculated by analyzing the timing diagram and compared with the reference index of coordination so as to prompt for correcting the swimming posture according to a comparison result.Type: GrantFiled: March 19, 2019Date of Patent: September 29, 2020Assignee: Industrial Technology Research InstituteInventors: Tzu-Yang Ting, Yu-Hua Chung, Chieh-Wei Feng, Yen-Ting Wu
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Publication number: 20200269113Abstract: A swimming posture correction method and a swimming posture correction system, adapted for a computing apparatus to correct a swimming posture of a swimmer using at least two gravity sensors, are provided. The gravity sensors are respectively disposed at ends of at least two limbs of the swimmer performing a relative stroke action. In the method, body parameters of the swimmer are obtained and a reference index of coordination for implementing a swimming posture suitable for the body parameters is captured. A stroke of the limb is monitored using the gravity sensors to obtain a timing diagram of the limbs performing a stroke promotion action. Then, an index of coordination of the swimmer is calculated by analyzing the timing diagram and compared with the reference index of coordination so as to prompt for correcting the swimming posture according to a comparison result.Type: ApplicationFiled: March 19, 2019Publication date: August 27, 2020Applicant: Industrial Technology Research InstituteInventors: Tzu-Yang Ting, Yu-Hua Chung, Chieh-Wei Feng, Yen-Ting Wu
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Publication number: 20200212033Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.Type: ApplicationFiled: May 8, 2019Publication date: July 2, 2020Applicant: Industrial Technology Research InstituteInventors: Yu-Hua Chung, Tai-Jui Wang, Chieh-Wei Feng
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Publication number: 20200063282Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.Type: ApplicationFiled: June 20, 2019Publication date: February 27, 2020Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chien-Hsun CHU, Chien-Chou TSENG, Ming-Huan YANG, Tai-Jui WANG, Yu-Hua CHUNG, Chieh-Wei FENG
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Publication number: 20190355713Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.Type: ApplicationFiled: November 8, 2018Publication date: November 21, 2019Applicant: Industrial Technology Research InstituteInventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Yu-Hua Chung
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Patent number: 10083989Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.Type: GrantFiled: July 14, 2016Date of Patent: September 25, 2018Assignee: Industrial Technology Research InstituteInventors: Tai-Jui Wang, Tsu-Chiang Chang, Yu-Hua Chung, Wei-Han Chen, Hsiao-Chiang Yao
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Publication number: 20170170207Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.Type: ApplicationFiled: July 14, 2016Publication date: June 15, 2017Inventors: Tai-Jui Wang, Tsu-Chiang Chang, Yu-Hua Chung, Wei-Han Chen, Hsiao-Chiang Yao