Abstract: A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate has source/drain regions and a channel region between the source/drain regions. The gate structure is over the channel region of the semiconductor substrate. The gate structure includes an interfacial layer, a zirconium-containing dielectric layer, and a gate electrode. The zirconium-containing dielectric layer is over the interfacial layer and is in tetragonal-phase. The gate electrode is over the zirconium-containing dielectric layer.

Abstract: A sub-circuit of a reconfigurable wireless receiver includes a down-conversion circuit and a plurality of filters. The down-conversion circuit applies down-conversion to a first signal, and generates and outputs a plurality of second signals each derived from down-converting the first signal. The filters are coupled to the down-conversion circuit, and apply filtering to the second signals for generating a plurality of filter outputs, respectively, wherein the filters includes a first filter and a second filter, and the first filter and the second filter have different filter architecture.

Abstract: An oscillator includes a first current source, a second current source, a first chopper circuit, a resistive component, a capacitive component, and a processing circuit. The first current source provides a first current. The second current source provides a second current. The first chopper circuit includes a first terminal coupled to the first current source, a second terminal coupled to the second current source, a third terminal coupled to the resistive component, and a fourth terminal coupled to the capacitive component. The processing circuit generates an output clock in response to a first voltage across the resistive component and a second voltage across the capacitive component. The first chopper circuit couples the first terminal and the second terminal to the third terminal and the fourth terminal, respectively and alternately. The resistive component and the capacitive component receive the first current and the second current, respectively and alternately.

Abstract: A control circuit for a main switch is provided. The control circuit includes an output voltage tracker, a main switch bias generator, and a reference current device. The output voltage tracker is coupled to the main output end and generates a first tracking voltage positively correlated to an output voltage. The main switch bias generator, in response to the first tracking voltage, generates a second tracking voltage substantially equal to the output voltage. The reference current device is coupled to the main switch bias generator and is used to generate a control voltage on a main control end. The reference current device is used to limit the maximum value of the output current. The main switch and a duplicating switching element of the main switch bias generator form a current mirror configuration circuit. The consuming current of the output voltage tracker is positively correlated to the output current.

Abstract: A control circuit for a main switch is provided. The control circuit includes an output voltage tracker, a main switch bias generator, and a reference current device. The output voltage tracker is coupled to the main output end and generates a first tracking voltage positively correlated to an output voltage. The main switch bias generator, in response to the first tracking voltage, generates a second tracking voltage substantially equal to the output voltage. The reference current device is coupled to the main switch bias generator and is used to generate a control voltage on a main control end. The reference current device is used to limit the maximum value of the output current. The main switch and a duplicating switching element of the main switch bias generator form a current mirror configuration circuit. The consuming current of the output voltage tracker is positively correlated to the output current.

Abstract: A floating gate non-volatile memory device includes at least one floating gate non-volatile memory cell including a semiconductor substrate, a gate stack unit, and a drain and source unit. The gate stack unit includes a tunnel oxide layer having a negative capacitance, a floating gate layer disposed on the tunnel oxide layer, a blocking oxide layer disposed on the floating gate layer and opposite to the tunnel oxide layer, and a control gate layer disposed on the blocking oxide layer and opposite to the floating gate layer. The drain and source unit is disposed in the semiconductor substrate and includes source and drain regions that are respectively disposed on two opposite sides of the gate stack unit.

Abstract: An audio system includes a reference voltage generation circuit to generate a digital encoding signal and generate an analog reference voltage according to the digital encoding signal, wherein, during a booting procedure and/or a shutdown procedure, the analog reference voltage is smoothly increased and/or decreased at a smooth rate related to a bit number of the digital encoding signal; a first analog operational amplifier for receiving the analog reference voltage to generate a common voltage, which is smoothly increased and/or decreased during the booting procedure and/or the shutdown procedure; and a differential analog operational amplifier pair, coupled to the first analog operational amplifier, for receiving a differential audio input signal pair and outputting a differential output voltage pair to drive a load, wherein, during the booting procedure and/or the shutdown procedure, the differential audio output signal pair is smoothly increased and/or decreased.

Abstract: The invention provides a power amplifier circuit capable of adjusting gain dynamically. The power amplifier circuit comprises a power supply unit configured to provide a power supply signal; an input power detection unit for receiving at least one input signal and the power supply signal, detecting the power of the input signal to generate a detection signal, and pulling up or down a bias signal by the detection signal; a power amplifier unit for receiving the input signal and the bias signal, adjusting the gain by the controlling of the bias signal, and amplifying the input signal by the adjusted gain to output at least one output signal. Therefore, the gain of power amplifier circuit will be adjusted dynamically by detecting the power of the input signal, so that the output signal conforming to the actual power may be outputted.

Abstract: The present invention provides a digital television signal reception system, comprising a chip having a low-noise amplifier and a master receiver, at least one slave receiver, and at least one local-oscillator leakage processing unit. The chip receives at least one digital input signal of television channel. The low-noise amplifier amplifies and sends the input signal of television channel to the master/slave receiver. The input signal of television channel is frequency-mixed by the master/slave receiver so as to output an output signal of second television channel and an output signal of second television channel. The local-oscillator leakage processing unit detects and removes local-oscillator leakage of the master receiver included in the output signal of second television channel, so as to avoid interference of the local leakage of master receiver on sensitivity of receiving the output signal of second television channel of slave receiver by the slave television.

Abstract: The invention provides a power amplifier circuit capable of adjusting gain dynamically. The power amplifier circuit comprises a power supply unit configured to provide a power supply signal; an input power detection unit for receiving at least one input signal and the power supply signal, detecting the power of the input signal to generate a detection signal, and pulling up or down a bias signal by the detection signal; a power amplifier unit for receiving the input signal and the bias signal, adjusting the gain by the controlling of the bias signal, and amplifying the input signal by the adjusted gain to output at least one output signal. Therefore, the gain of power amplifier circuit will be adjusted dynamically by detecting the power of the input signal, so that the output signal conforming to the actual power may be outputted.

Abstract: The present invention provides a digital television signal reception system, comprising a chip having a low-noise amplifier and a master receiver, at least one slave receiver, and at least one local-oscillator leakage processing unit. The chip receives at least one digital input signal of television channel. The low-noise amplifier amplifies and sends the input signal of television channel to the master/slave receiver. The input signal of television channel is frequency-mixed by the master/slave receiver so as to output an output signal of second television channel and an output signal of second television channel. The local-oscillator leakage processing unit detects and removes local-oscillator leakage of the master receiver included in the output signal of second television channel, so as to avoid interference of the local leakage of master receiver on sensitivity of receiving the output signal of second television channel of slave receiver by the slave television.

Abstract: A chargeable device is disclosed. The chargeable device of the present invention comprises a main circuit module with a coil, and at least one integrated circuit module with a compensation capacitor operated with the coil.

Abstract: A gain control circuit of the wireless receiver comprises a plurality of stages-amplifier, an analog gain control circuit, and a digital gain control circuit, wherein the analog gain control circuit generates an analog controlling voltage for regulating the gain of the post-amplifier by an analog gain controlling process, and the digital gain control circuit is used for determining a plurality of gain curves for the pre-amplifier, and the gain curves are all operating between the first default voltage and second default voltage. While the analog controlling voltage is over the first default voltage or second default voltage, the gain curve will be switched, thereby, the analog gain controlling process can be with the digital gain controlling process therein for improving the linearity of the gain regulation and reducing the transient response during the gain switching process.

Abstract: An amplifier gain control circuit for the wireless transceiver comprises at least one amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC) and a bias circuit, wherein the ADC is used for receiving an analog gain control voltage to generate a digital control signal that can be used for controlling the gain of the amplifier, the DAC is used for receiving the digital signal to generate an analog signal, and the bias circuit is used for receiving the analog signal and the analog gain control voltage to further fine-tune the gain of the amplifier by the analog process for correcting the least bit error during the digital process, therefore, the amplifier during the gain adjustment will be prevented to operate in the nonlinear area.

Abstract: A gain control circuit of the wireless receiver comprises a plurality of stages-amplifier, an analog gain control circuit, and a digital gain control circuit, wherein the analog gain control circuit generates an analog controlling voltage for regulating the gain of the post-amplifier by an analog gain controlling process, and the digital gain control circuit is used for determining a plurality of gain curves for the pre-amplifier, and the gain curves are all operating between the first default voltage and second default voltage. While the analog controlling voltage is over the first default voltage or second default voltage, the gain curve will be switched, thereby, the analog gain controlling process can be with the digital gain controlling process therein for improving the linearity of the gain regulation and reducing the transient response during the gain switching process.

Abstract: An amplifier gain control circuit for the wireless transceiver comprises at least one amplifier, an analog to digital converter (ADC), a digital to analog converter (DAC) and a bias circuit, wherein the ADC is used for receiving an analog gain control voltage to generate a digital control signal that can be used for controlling the gain of the amplifier, the DAC is used for receiving the digital signal to generate an analog signal, and the bias circuit is used for receiving the analog signal and the analog gain control voltage to further fine-tune the gain of the amplifier by the analog process for correcting the least bit error during the digital process, therefore, the amplifier during the gain adjustment will be prevented to operate in the nonlinear area.

Abstract: A voltage reference circuit comprises a current mirror set, a first resistor, a first MOS transistor, and a second MOS transistor. The output end of the current mirror set is coupled to a first resistor, and the node of the current mirror set is coupled to the first MOS transistor, furthermore, the second MOS transistor is coupled to the first MOS transistor, and the first end and the gate of the second MOS transistor are coupled each other, such that a stable voltage reference will be obtained between the first MOS transistor and the second MOS transistor.

Abstract: An extended range received signal strength indicator module includes input lines connected to a variable gain amplifier, which passes the amplified RF signal to a polyphase, which in turn passes the filtered signal to a series of RSSI stages. Each RSSI stage includes a log amplifier and outputs an amplified current to a current summer as well as to the next RSSI stage in the series. The current summer outputs the sum of the received currents to RSSI_OUT. An additional frequency filter and RSSI stage with inputs connected to the input lines before the variable gain amplifier that outputs the modified current to the current summer is also included. A control circuit switches the additional RSSI stage on or off as determined by a detection circuit that monitors the value of RSSI_OUT.

Abstract: A demodulation method and apparatus are provided. An RF signal is down converted to generate a first in-phase signal and a first quadrature signal of a first frequency. Limiting amplification is performed on the first in-phase signal and the first quadrature signal to generate a second in-phase signal and a second quadrature signal. The frequency of the second in-phase and quadrature signals are up converted to a third in-phase signal and a quadrature signal of a second frequency. The third in-phase and quadrature signals are up converted to generate an intermediate frequency (IF) signal of a third frequency.

Abstract: A gain control circuit and a variable gain amplifier using the same. In the variable gain amplifier, gain control circuit generates a gain control voltage according to a control voltage, and a gain variable amplification unit is coupled to the gain control circuit and an input voltage to adjust an output signal output to a load according to the gain control voltage. In the gain control circuit, a level shifter with a constant current source generates a first voltage according to a control voltage. A first temperature compensation unit has a first temperature-controlled current source, and generates a second voltage according to a present operating temperature. A voltage conversion unit coupled to the level shifter and the first temperature compensation unit generates a gain control voltage according to the first and second voltages.