Patents by Inventor Yu-Hua YEN

Yu-Hua YEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Deep trench isolation structure in semiconductor device
    Patent number: 11201082
    Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.
    Type: Grant
    Filed: November 16, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • DEEP TRENCH ISOLATION STRUCTURE IN SEMICONDUCTOR DEVICE
    Publication number: 20200083092
    Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.
    Type: Application
    Filed: November 16, 2019
    Publication date: March 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua YEN, Ching-Hung KAO, Po-Jen WANG, Tsung-Han TSAI
  • Deep trench isolation structure in semiconductor device
    Patent number: 10483153
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • DEEP TRENCH ISOLATION STRUCTURE IN SEMICONDUCTOR DEVICE
    Publication number: 20190148219
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua YEN, Ching-Hung KAO, Po-Jen WANG, Tsung-Han TSAI
  • Formation of contact/via hole with self-alignment
    Patent number: 9805934
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung Jen, Yu-Hua Yen
  • FORMATION OF CONTACT/VIA HOLE WITH SELF-ALIGNMENT
    Publication number: 20150140796
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung JEN, Yu-Hua YEN