Patents by Inventor Yu-Huang Yeh
Yu-Huang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11918882Abstract: An interactive exercise apparatus for guiding a user to perform an exercise includes a display device and a detecting device. The display device is configured to display video imagery which shows an instructor image and at least one motion check image. The motion check image corresponds to a predetermined one of a plurality of body parts of the user, which has a motion guide track and a motion achievement evaluation. The detecting device is configured to detect displacement of the body parts. The motion guide track is displayed on a predetermined position of the video imagery with a predetermined track pattern, corresponding to a movement path of the predetermined body part when the user follows movements demonstrated by the instructor image to perform the exercise. The motion achievement evaluation indicates a matching degree determined according to the displacement of the predetermined body part detected by the detecting device.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: Johnson Health Tech Co., Ltd.Inventors: Hsin-Huang Chiang, Yu-Chieh Lee, Ning Chuang, Wei-Ting Weng, Cheng-Ho Yeh
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Patent number: 11778830Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.Type: GrantFiled: November 3, 2022Date of Patent: October 3, 2023Assignee: United Microelectronics Corp.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang
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Publication number: 20230046058Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.Type: ApplicationFiled: November 3, 2022Publication date: February 16, 2023Applicant: United Microelectronics Corp.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang
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Patent number: 11581325Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.Type: GrantFiled: March 15, 2021Date of Patent: February 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang
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Publication number: 20220223612Abstract: A memory structure including a substrate, a first dielectric layer, a second dielectric layer, a charge storage layer, an oxide layer, and a conductive layer is provided. The first dielectric layer is disposed on the substrate. The second dielectric layer is disposed on the first dielectric layer. The charge storage layer is disposed between the first dielectric layer and the second dielectric layer. The oxide layer is located at two ends of the charge storage layer and is disposed between the first dielectric layer and the second dielectric layer. The conductive layer is disposed on the second dielectric layer.Type: ApplicationFiled: March 15, 2021Publication date: July 14, 2022Applicant: United Microelectronics Corp.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang
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Patent number: 11348805Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: GrantFiled: October 9, 2020Date of Patent: May 31, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Publication number: 20210028025Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: ApplicationFiled: October 9, 2020Publication date: January 28, 2021Applicant: United Microelectronics Corp.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Patent number: 10847378Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: GrantFiled: November 1, 2018Date of Patent: November 24, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Hung Chen, Yu-Huang Yeh, Chuan-Fu Wang, Chin-Chin Tsai
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Patent number: 10770565Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.Type: GrantFiled: September 6, 2018Date of Patent: September 8, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsueh-Chun Hsiao, Tzu-Yun Chang, Chuan-Fu Wang, Yu-Huang Yeh
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Publication number: 20200144072Abstract: A semiconductor device includes a substrate, having a cell region and a core region. A plurality of gate structures is disposed on the substrate in the cell region. Each of the gate structures has a spacer on a sidewall of the gate structures. The gate structure includes a charge storage layer, on the substrate; a first polysilicon layer on the charge storage layer; and a mask layer on the first polysilicon layer, the mask layer comprising a first polishing stop layer on top. A preliminary material layer also with the first polishing stop layer on top is disposed on the substrate at the core region. A second polysilicon layer is filled between the gate structures at the cell region. A second polishing stop layer is on the second polysilicon layer. The first polishing stop layer and the second polishing stop layer are same material and same height.Type: ApplicationFiled: November 1, 2018Publication date: May 7, 2020Inventors: CHIA-HUNG CHEN, YU-HUANG YEH, CHUAN-FU WANG, CHIN-CHIN TSAI
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Publication number: 20200083344Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Applicant: United Microelectronics Corp.Inventors: Hsueh-Chun Hsiao, Tzu-Yun Chang, Chuan-Fu Wang, Yu-Huang Yeh
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Patent number: 8436411Abstract: A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region.Type: GrantFiled: January 6, 2009Date of Patent: May 7, 2013Assignee: United Microelectronics Corp.Inventors: Sung-Bin Lin, Yuan-Hsiang Chang, Yu-Huang Yeh, Che-Lieh Lin
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Publication number: 20100171165Abstract: A non-volatile memory including a substrate, two first conductive layers, a second conductive layer, a first dielectric layer, a second dielectric layer and two heavily doped regions is provided. The substrate has at least two isolation structures therein and an active region between the isolation structures. The first conductive layers are respectively disposed on the isolation structures. The second conductive layer is disposed on the substrate and covering a portion of the active region and a portion of each first conductive layer. The first dielectric layer is disposed between each first conductive layer and the second conductive layer. The second dielectric layer is disposed between the second conductive layer in the active region and the substrate. The heavily doped regions are disposed in the substrate beside the second conductive layer in the active region.Type: ApplicationFiled: January 6, 2009Publication date: July 8, 2010Applicant: United Microelectronics Corp.Inventors: Sung-Bin Lin, Yuan-Hsiang Chang, Yu-Huang Yeh, Che-Lieh Lin