Patents by Inventor Yu-Hui Lin

Yu-Hui Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149477
    Abstract: A photonic assembly includes: an electronic integrated circuits (EIC) die including a semiconductor substrate, semiconductor devices located on a horizontal surface of the semiconductor substrate, first dielectric material layers embedding first metal interconnect structures, a dielectric pillar structure vertically extending through each layer selected from the first dielectric material layers, a first bonding-level dielectric layer embedding first metal bonding pads, wherein a first subset of the first metal bonding pads has an areal overlap with the dielectric pillar structure in a plan view; and a photonic integrated circuits (PIC) die including waveguides, photonic devices, second dielectric material layers embedding second metal interconnect structures, a second bonding-level dielectric layer embedding second metal bonding pads, wherein the second metal bonding pads are bonded to the first metal bonding pads.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 8, 2025
    Inventors: Yu-Hung Lin, Chih-Hao Yu, Wei-Ming Wang, Chen Chen, Chia-Hui Lin, Ren-Fen Tsui, Chen-Hua Yu
  • Publication number: 20250141084
    Abstract: A transparent antenna is provided. A transparent antenna includes a transparent dielectric substrate, a plurality of antenna conductive layers, a feeding layer and a plurality of grounding layers. The antenna conductive layers are disposed on a first surface of the transparent dielectric substrate. The feeding layer is disposed on the first surface of the transparent dielectric substrate and is connected to the antenna conductive layers. Each of the antenna conductive layer, the feeding layer and the grounding layer is a mesh structure. The antenna conductive layers and the grounding layers corresponding thereto form a plurality of antenna units. The antenna conductive layers of the antenna units are not all the same; or the grounding layers of the antenna units are not all the same.
    Type: Application
    Filed: October 21, 2024
    Publication date: May 1, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Yang TSAI, Bing-Hsun LI, Kuang-Hui SHIH, Yu-Ching LIN
  • Patent number: 12278631
    Abstract: A main board, a hot plug control signal generator, and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch is operated based on an operation power to generate a hot plug control signal. The latch sets the hot plug control signal to a disabled first logic value, and latches the hot plug control signal at the first logic value.
    Type: Grant
    Filed: May 29, 2024
    Date of Patent: April 15, 2025
    Assignee: Wiwynn Corporation
    Inventors: Wei-Fang Chang, Yu-Chun Chen, Nan-Huan Lin, Chung-Hui Yen, Shi-Rui Chen
  • Publication number: 20250118612
    Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen Chen, Yu-Hung Lin, Chih-Hao Yu, Wei-Ming Wang, Chia-Hui Lin, Shih-Peng Tai
  • Patent number: 12243872
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Huang Huang, Yu-Ling Cheng, Shun-Hui Yang, An Chyi Wei, Chia-Jen Chen, Shang-Shuo Huang, Chia-I Lin, Chih-Chang Hung
  • Publication number: 20250063744
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 20, 2025
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20250063743
    Abstract: Some implementations described herein provide techniques and apparatuses for an integrated circuit device including a trench capacitor structure that has a merged region. A material filling the merged region is different than a material that is included in electrode layers of the trench capacitor structure. Furthermore, the material filling the merged region includes a coefficient of thermal expansion and a modulus of elasticity that, in combination with the architecture of the trench capacitor structure, reduce thermally induced stresses and/or strains within the integrated circuit device relative to another integrated circuit device having a trench capacitor structure including a merged region and electrode layers of a same material.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Inventors: Shu-Hui SU, Hsin-Li CHENG, YingKit Felix TSUI, Tuo-Hsin CHIEN, Jyun-Ying LIN, Shi-Min WU, Yu-Chi CHANG, Ting-Chen HSU
  • Publication number: 20250056746
    Abstract: An electronic device including a device housing, a cable, a cable positioning structure, and a housing restriction structure is provided. The device housing includes a through hole. The through hole includes a central region, a first channel region, and a second channel region. The cable passes through the device housing. The cable positioning structure is disposed on the cable. The cable positioning structure includes a first protrusion and a second protrusion. The cable positioning structure is adapted to be rotated between a first orientation and a second orientation relative to the device housing. The housing restriction structure is disposed on the device housing. The housing restriction structure includes a first restrain member and a first stopper. In a positioned state, the cable positioning structure is in the second orientation. The first restrain member and the first stopper restrict the cable positioning structure.
    Type: Application
    Filed: July 18, 2024
    Publication date: February 13, 2025
    Inventors: Che-Cheng WU, Chen-Wei HUANG, Yu-Hsiang LIN, Ya-Hui LO
  • Publication number: 20250054900
    Abstract: A package structure includes a circuit substrate, a package unit, a thermal interface material and a cover. The package unit is disposed on and electrically connected with the circuit substrate. The package unit includes a first surface facing the circuit substrate and a second surface opposite to the first surface. A underfill is disposed between the package unit and the circuit substrate, surrounding the package unit and partially covering sidewalls of the package unit. The cover is disposed over the package unit and over the circuit substrate. An adhesive is disposed on the circuit substrate and between the cover and the circuit substrate. The thermal interface material includes a metal-type thermal interface material and is disposed between the cover and the package unit. The thermal interface material physically contacts the second surface and the sidewalls of the package unit and physically contacts the underfill.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yen Lan, Chih-Chien Pan, Pu Wang, Li-Hui Cheng, Ying-Ching Shih, Yu-Wei Lin
  • Publication number: 20250044708
    Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.
    Type: Application
    Filed: October 18, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Gun LIU, Huicheng CHANG, Chia-Cheng CHEN, Jyu-Horng SHIEH, Liang-Yin CHEN, Shu-Huei SUEN, Wei-Liang LIN, Ya Hui CHANG, Yi-Nien SU, Yung-Sung YEN, Chia-Fong CHANG, Ya-Wen YEH, Yu-Tien SHEN
  • Patent number: 12142342
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: November 12, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Publication number: 20240220210
    Abstract: A modulo divider and a modulo division operation method for binary data are provided, including: converting a first variant and a second variant to a variant set according to a first mapping table; generating a fifth variant and a sixth variant according to the variant set; generating a seventh variant and an eighth variant according to the variant set; updating the first variant according to one of the fifth variant and the sixth variant and updating the second variant according to the other one of the fifth variant and the sixth variant; updating the third variant according to one of the seventh variant and the eighth variant and updating the fourth variant according to the other one of the seventh variant and the eighth variant; and outputting the third variant as a result of a modulo division operation in response to determining the updating of the third variant being finished.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 4, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Hsiang Yang, Liang-Hsin Lin, Yu-Ling Kang, Yu-Hui Lin, Chih-Ming Lai
  • Patent number: 11741189
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: August 29, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Publication number: 20230267973
    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.
    Type: Application
    Filed: December 5, 2022
    Publication date: August 24, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Fu-Cheng Tsai, Tuo-Hung Hou, Jian-Wei Su, Yu-Hui Lin, Chih-Ming Lai
  • Publication number: 20230153375
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Patent number: 11599600
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.
    Type: Grant
    Filed: September 6, 2020
    Date of Patent: March 7, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Patent number: 11423983
    Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 23, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Sheng Lin, Sih-Han Li, Yu-Hui Lin, Jian-Wei Su
  • Publication number: 20220223202
    Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.
    Type: Application
    Filed: May 17, 2021
    Publication date: July 14, 2022
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Sheng LIN, Sih-Han LI, Yu-Hui LIN, Jian-Wei SU
  • Publication number: 20210397675
    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.
    Type: Application
    Filed: September 6, 2020
    Publication date: December 23, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Jian-Wei Su, Tuo-Hung Hou, Sih-Han Li, Fu-Cheng Tsai, Yu-Hui Lin
  • Patent number: 10523257
    Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 31, 2019
    Assignee: HTC Corporation
    Inventors: Hsin-Hao Lee, Cheng-Lin Wang, Ernest Euan Tien, Yin-Chou Chen, Tsung-Peng Lin, Cheng-Yen Lee, Yu-Hui Lin, Chang-Hua Wei, Jen-Yang Chang, Shih-Hsiu Lee, Jui Hsiang Lin, Hung Chuan Wen, Yen-Cheng Lin, Yen-Yi Lee, Ting-An Chien, Hsin-Hui Huang, Sheng Cherng Lin, Yung-Lung Chang