Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.

Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.

Abstract: A method includes fabricating a semiconductor device, wherein the method includes depositing a coating layer on a first region and a second region under a loading condition such that a height of the coating layer in the first region is greater than a height of the coating layer in the second region. The method also includes applying processing gas to the coating layer to remove an upper portion of the coating layer such that a height of the coating layer in the first region is a same as a height of the coating layer in the second region.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A memory device for in-memory computation includes data channels, a memory cell array, a maximum accumulated weight generating array, a minimum accumulated weight generating array, a reference generator and a comparator. The data channels are selectively enabled according to data input. The memory cell array generates an accumulated data weight value according to the quantity of enabled data channels, a first resistance and a second resistance. The maximum accumulated weight generating array generates a maximum accumulated weight value according to the quantity of enabled data channels and the first resistance. The minimum accumulated weight generating array generates a minimum accumulated weight value according to the quantity of enabled data channels and the second resistance. The reference generator generates reference value(s) according to the maximum and minimum accumulated weight values.

Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: A backlight module including a light source, a reflector, a chamber, and a block plate is provided. The light source has at least one light unit arranged along a first direction. The reflector extends along the first direction and a curve opposite the light unit is formed on a cross section perpendicular to the first direction. The reflector has a first end and a second end opposite to each other. The first end extends toward the light source while the second end forms a light exit with the light source. The chamber has a light entrance end facing the light exit to receive light reflected by the reflector. The block plate is disposed between the light unit and a light-receiving surface of the chamber to reduce the light directly reflected to the light-receiving surface of the chamber by the reflector.

Abstract: A backlight module including a light source, a reflector, a chamber, and a block plate is provided. The light source has at least one light unit arranged along a first direction. The reflector extends along the first direction and a curve opposite the light unit is formed on a cross section perpendicular to the first direction. The reflector has a first end and a second end opposite to each other. The first end extends toward the light source while the second end forms a light exit with the light source. The chamber has a light entrance end facing the light exit to receive light reflected by the reflector. The block plate is disposed between the light unit and a light-receiving surface of the chamber to reduce the light directly reflected to the light-receiving surface of the chamber by the reflector.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.

Abstract: Aspects of the technology relate to a cover (e.g., for a handheld electronic device). The cover may include a cover body configured for securement to a handheld electronic device and comprising an accessory attachment area, wherein the accessory attachment area includes a plurality of receivers, and wherein the accessory attachment area is configured for coupling with an accessory in at least one of a plurality of orientations. In some aspects, each receiver further includes a space recessed into the cover body that is bounded, at least partially, by a recess wall, wherein each receiver includes an engagement surface configured for abutting engagement with a projection associated with an accessory when the projection is disposed in a secured configuration within a respective space. An electrical device cover and various attachment devices are also provided.