Patents by Inventor Yu Hui Wu

Yu Hui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200205300
    Abstract: A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 25, 2020
    Inventor: Yu-Hui WU
  • Patent number: 10692807
    Abstract: A chip-on-film (COF) package structure includes a first COF and a second COF. The first COF includes a first flexible substrate having a first external terminal and a first internal terminal opposite to each other, first outer leads disposed at the first external terminal, first inner leads disposed at the first internal terminal, and a first chip disposed between the first external terminal and the first internal terminal. The second COF includes a second flexible substrate having a second external terminal and a second internal terminal opposite to each other, second outer leads disposed at the second external terminal, second inner leads disposed at the second internal terminal, and a second chip disposed between the second external terminal and the second internal terminal. The first COF is partially overlapped with the second COF. A display device having the COF package structure is also provided.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 23, 2020
    Assignee: Au Optronics Corporation
    Inventors: Chang-Hui Wu, Yu-Huei Jiang, Hsiao-Chung Cheng
  • Publication number: 20200194321
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 18, 2020
    Applicant: United Microelectronics Corp.
    Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Patent number: 10670784
    Abstract: A light filter structure is provided. The light filter structure includes a first filter layer disposed over the substrate. The first filter layer has a transmittance greater than 50% in a first waveband, wherein the first filter layer is an interference-type filter. The light filter structure further includes a second filter layer disposed over the substrate. The second filter layer has a transmittance greater than 50% in a second waveband, wherein the second filter layer is an absorption-type filter. The first waveband partially overlaps the second waveband at the wavelength in a third waveband, and the third waveband is in an IR region. Furthermore, an image sensor used as a time-of-flight image sensor is also provided.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 2, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Wei-Ko Wang, Yu-Jen Chen, Chia-Hui Wu
  • Publication number: 20200161518
    Abstract: A light-emitting diode package including a carrier structure, a patterned conductive layer, at least one chip, a dielectric layer, at least one first conductive via, a build-up circuit structure, and at least one light-emitting diode is provided. The patterned conductive layer is disposed on the carrier structure. The chip is disposed on the carrier structure. The dielectric layer is disposed on the carrier structure and encapsulates the chip and the patterned conductive layer. The first conductive via penetrates the dielectric layer and is electrically connected to the patterned conductive layer. The build-up circuit structure is disposed on the dielectric layer and electrically connected to the first conductive via. The light-emitting diode is disposed on the build-up circuit structure.
    Type: Application
    Filed: February 21, 2019
    Publication date: May 21, 2020
    Applicant: Unimicron Technology Corp.
    Inventors: Yi-Cheng Lin, Yu-Hua Chen, Chun-Hsien Chien, Chien-Chou Chen, Cheng-Hui Wu
  • Publication number: 20200163223
    Abstract: A method of manufacturing first and second component carriers includes: i) providing a separation component comprising a first separation surface and a second separation surface being opposed to the first separation surface, ii) coupling a first base structure having a first cavity with the first separation surface, iii) coupling a second base structure having a second cavity with the second separation surface, iv) placing a first electronic component in the first cavity, v) connecting the first base structure with the first electronic component to form the first component carrier, vi) placing a second electronic component in the second cavity, vii) connecting the second base structure with the second electronic component to form the second component carrier, viii) separating the first component carrier from the first separation surface of the separation component, and ix) separating the second component carrier from the second separation surface of the separation component.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 21, 2020
    Inventors: Jeesoo Mok, Seok Kim Tay, Mikael Tuominen, Yu-Hui Wu
  • Patent number: 10658348
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200152553
    Abstract: A chip-on-film (COF) package structure includes a first COF and a second COF. The first COF includes a first flexible substrate having a first external terminal and a first internal terminal opposite to each other, first outer leads disposed at the first external terminal, first inner leads disposed at the first internal terminal, and a first chip disposed between the first external terminal and the first internal terminal. The second COF includes a second flexible substrate having a second external terminal and a second internal terminal opposite to each other, second outer leads disposed at the second external terminal, second inner leads disposed at the second internal terminal, and a second chip disposed between the second external terminal and the second internal terminal. The first COF is partially overlapped with the second COF. A display device having the COF package structure is also provided.
    Type: Application
    Filed: February 26, 2019
    Publication date: May 14, 2020
    Applicant: Au Optronics Corporation
    Inventors: Chang-Hui Wu, Yu-Huei Jiang, Hsiao-Chung Cheng
  • Patent number: 10629748
    Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pengfei Guo, Shao-Hui Wu, Hai Biao Yao, Yu-Cheng Tung, Yuanli Ding, Zhibiao Zhou
  • Patent number: 10615811
    Abstract: A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Hui Wu, Yu-Chang Chen, Chih-Lung Chen, Shih-Hsiung Huang
  • Publication number: 20200105638
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: February 4, 2019
    Publication date: April 2, 2020
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105730
    Abstract: A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Chih-Hsuan Tai, Chi-Hui Lai, Ying-Cheng Tseng, Ban-Li Wu, Ting-Ting Kuo, Yu-Chih Huang, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200105738
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 2, 2020
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200096852
    Abstract: A projector includes an optical engine module, a projection lens module, a heat dissipation module, and a laser module. The laser module includes a positioning member and a laser unit fixed to the positioning member, wherein a positioning member includes a main plate portion and two shoulder portions, the main plate portion includes a first upper surface and a first lower surface opposite to each other, a first front surface and a first rear surface opposite to each other, and a first left side surface and a first right side surface opposite to each other, and the two shoulder portions extend on a plane of the first upper surface from the first left side surface and the first right side surface of the main board portion, respectively. A laser module is also provided.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 26, 2020
    Inventors: CHUN-HSIEN WU, KUEI-JU WENG, CHIH-HUI CHANG, YU-CHANG CHANG, FU-SHUN KAO
  • Publication number: 20200058626
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20200055895
    Abstract: The present invention relates to a compound simultaneously having triple activities of thrombolysis, antithrombosis and free radical scavenging, as well as the preparation method, composition, and applications thereof. The compound is represented by the formula I shown below: wherein the definitions of T, Q, R1 and R2 are described herein. The compound of the present invention simultaneously has triple functions of thrombolysis, free radical scavenging and thrombus-targeting/antithrombosis. The present invention also relates to a pharmaceutical composition comprising the compound, and a preparation method and a nanostructure of the compound.
    Type: Application
    Filed: July 9, 2019
    Publication date: February 20, 2020
    Inventors: Shi-Qi PENG, Ming ZHAO, Jian-Hui WU, Yu-Ji WANG, Qi-Qi FENG
  • Publication number: 20200045825
    Abstract: A component carrier includes a base structure with component carrier material and forming a cavity, a component embedded in the cavity, a first electrically insulating layer structure connected to a front side of the base structure and to the component and at least partially filling a gap between the component and the base structure, and a second electrically insulating layer structure connected to the first electrically insulating layer structure at a connection surface of the first electrically insulating layer structure. The connection surface opposes an opposing surface of the second electrically insulating layer structure faces away from the first electrically insulating layer structure.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 6, 2020
    Inventors: Yu-Hui Wu, Christopher Katzko
  • Publication number: 20200035723
    Abstract: A method for forming an image sensor device structure is provided. The method includes forming a light-sensing region in a substrate, and forming an interconnect structure below a first surface of the substrate. The method also includes forming a trench in the light-sensing region from a second surface of the substrate, and forming a doping layer in the trench. The method includes forming an oxide layer in the trench and on the doping layer to form a doping region, and the doping region is inserted into the light-sensing region.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Yen-Ting CHIANG, Chun-Yuan CHEN, Hsiao-Hui TSENG, Yu-Jen WANG, Shyh-Fann TING, Wei-Chuang WU, Jen-Cheng LIU, Dun-Nian YAUNG
  • Patent number: 10475932
    Abstract: A transistor structure includes a first oxide semiconductor layer, a source structure and a drain structure, and a second oxide semiconductor layer. The first oxide semiconductor layer is doped with sulfur. The source structure and the drain structure are disposed on the first oxide semiconductor layer, and a region of the first oxide semiconductor layer between the source structure and the drain structure forms a channel region. The second oxide semiconductor layer doped with sulfur is at least formed on the channel region of the first oxide semiconductor layer.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: November 12, 2019
    Assignee: Untied Microelectronics Corp.
    Inventors: Shao-Hui Wu, Yu-Cheng Tung
  • Patent number: 10475828
    Abstract: An image sensor device structure is provided. The image sensor device structure includes a substrate, and the substrate is doped with a first conductivity type. The image sensor device structure includes a light-sensing region formed in the substrate, and the light-sensing region is doped with a second conductivity type that is different from the first conductivity type. The image sensor device structure further includes a doping region extended into the light-sensing region, and the doping region is doped with the first conductivity type. The image sensor device structure also includes a plurality of color filters formed on the doping region.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chiang, Chun-Yuan Chen, Hsiao-Hui Tseng, Yu-Jen Wang, Shyh-Fann Ting, Wei-Chuang Wu, Jen-Cheng Liu, Dun-Nian Yaung