Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract: A HIT solar cell is provided, including a p-type crystalline silicon substrate having a light-receiving surface, a first intrinsic amorphous silicon thin-film layer formed on the light-receiving surface of the p-type crystalline silicon substrate, an n-type amorphous oxide layer formed on the first intrinsic amorphous silicon thin-film layer, and a first transparent conductive layer formed on the n-type amorphous oxide layer. In the HIT solar cell, the n-type amorphous oxide layer can be directly formed, without forming the first intrinsic amorphous silicon thin-film layer, and the n-type amorphous oxide layer can be divided into an n?-type amorphous oxide layer and an n+-type amorphous oxide layer that are formed sequentially.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract: A manufacturing method of an array substrate includes following steps. A first photolithography process is performed to form a gate electrode on a substrate. A gate insulating layer is formed to cover the substrate and the gate electrode. A second photolithography process is performed to form a patterned semiconductor layer and a patterned etching stop layer. A semiconductor layer and an etching stop layer are successively formed on the gate insulating layer, and a second patterned photoresist is formed on the etching stop layer. The etching stop layer uncovered by the second patterned photoresist is removed. The semiconductor layer uncovered by the second patterned photoresist is removed for forming the patterned semiconductor on the gate insulating layer. A patterned etching stop layer is formed on the patterned semiconductor layer by etching the second patterned photoresist and the etching stop layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.

Abstract: The present invention is related to a biodegradable carrier with adjustable zeta potentials and particle sizes, a method for making the same, and a pharmaceutical composition comprising the same. In such a method, a first solution comprising a first biodegradable macromolecule is prepared, and a second solution comprising a second biodegradable macromolecule is also prepared according to a desired zeta potential of a biodegradable carrier and further added into the first solution to form a mixture solution. The biodegradable carrier with the desired zeta potentials is formed by the attraction force between the different electric properties. Then, the mole number of the first biodegradable macromolecule and the second biodegradable macromolecule in the mixture solution are proportionally adjusted according to a desired particle size of the biodegradable carrier. Therefore, the zeta potential and the particle size of the biodegradable carrier are adjustable artificially.

Abstract: The present invention is related to a biodegradable high-efficiency dengue vaccine, a method for making the same, and a pharmaceutical composition comprising the same. The biodegradable high-efficiency dengue vaccine comprises a biodegradable nanocomplex with electric properties holding a dengue viral protein inside. An organism has antibody responses after vaccination with the biodegradable nanocomplex twice. Accordingly, in comparison with the Alum adjuvant and Ribi adjuvant used in the traditional dengue vaccine of the prior art, the vaccination times in the present invention is decreased to further reduce the vaccination cost, so the biodegradable high-efficiency dengue vaccine is good for being a commercial vaccine.

Abstract: A method and a system for managing cache files, adapted for a local end apparatus to manage files cached from a service end apparatus, are provided. In the method, a file is divided into a plurality of segments, and a part of the segments are downloaded from the service end apparatus and stored in the local end apparatus. Then, the segments of the file to be downloaded are increased or decreased according to a utility rate of the file.

Abstract: A method for manufacturing thin film solar cells, includes forming a light permeable first electrode layer in the back light surface of a glass substrate, and formed in the first electrode layer a plurality of first openings for exposing a part of the back light surface therefrom; forming a photoelectric conversion layer on the first electrode layer and the exposed back light surface, and forming a plurality of second openings in the photoelectric conversion layer for exposing a part of the first electrode layer therefrom; and forming a glistening second electrode layer having a plurality of third openings formed therein, wherein the second electrode layer comprises a conductive colloid comprised of non-diffractive fillings and polymeric base material.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A manufacturing method for a Zinc Oxide (ZnO) piezoelectric thin-film with high C-axis orientation comprises the steps of providing a substrate having a base, a SiO2 layer and a Si3N4 layer; forming a bottom electrode layer on the Si3N4 layer; patterning the bottom electrode layer; sputtering a Zinc Oxide layer on the Si3N4 layer and the bottom electrode layer; forming a photoresist layer on the Si3N4 layer and the Zinc Oxide layer; patterning the photoresist layer to reveal the Zinc Oxide layer; forming a top electrode layer on the Zinc Oxide layer and the photoresist layer; removing the photoresist layer and the top electrode layer formed on the photoresist layer, and the top electrode layer formed on the Zinc Oxide layer can be remained; and patterning the Si3N4 layer to form a recess that reveals the base of the substrate.

Abstract: A manufacturing method of an array substrate includes the following steps. A first conductive layer, a gate insulating layer, a semiconductor layer, an etching stop layer, and a first patterned photoresist are successively formed on a substrate. The etching stop layer and the semiconductor layer uncovered by the first patterned photoresist are then removed by a first etching process. A patterned gate insulating layer and a patterned etching stop layer are then formed through a second etching process. The first conductive layer uncovered by the patterned gate insulating layer is then removed to form a gate electrode. The semiconductor layer uncovered by the patterned etching stop layer is then removed to form a patterned semiconductor layer and partially expose the patterned gate insulating layer.

Abstract: A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%.

Abstract: A method for manufacturing a P-I-N microcrystalline silicon structure for thin-film solar cells, includes the steps of: (a) forming a P-type layer; (b) forming an I-type layer including a plurality of sub-layers successively stacked on the P-type layer using gas mixtures including fluoride and hydride that have different gas ratios, respectively; and (c) forming an N-type layer on the I-type layer. First, second, and third I-type sub-layers may be formed on the P-type layer using gas mixtures including fluoride and hydride at a first, second, and third gas ratios, respectively. Then, advantageously, the third gas ratio may be larger than the second gas ratio and the second gas ratio may be larger than the first gas ratio, and the first gas ratio may be 8%, the second gas ratio may range between 15% and 35%, and the third gas ratio may range between 35% and 50%.

Abstract: A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.