Abstract: The present disclosure relates to a peritoneal cavity-bladder connecting catheter for ascites drainage. The peritoneal cavity-bladder connecting catheter for ascites drainage includes a peritoneal cavity position part positioned on the side of a peritoneal cavity by passing through a bladder wall located between the peritoneal cavity and a bladder, the peritoneal cavity position part having inlets through which ascites flow into an inner space and being formed as a film that surrounds the inner space, and a bladder position part integrally formed with the peritoneal cavity position part and positioned on the side of the bladder located on the side of the bladder wall opposite to the peritoneal cavity, the bladder position part having outlets through ascites flowed into the peritoneal cavity position part are discharged to outside, and being configured to form a closed inner space together with the peritoneal cavity position part.

Abstract: A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).

Abstract: A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).