Patents by Inventor Yu-Hwan Jung

Yu-Hwan Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240308323
    Abstract: A battery pack comprises a plurality of battery modules. Each battery module of the plurality of battery modules includes: a stacked structure including a plurality of stacked battery cells; and a front cover and a rear cover respectively disposed on a front side and a rear side of the stacked structure, configured to cover the stacked structure, and including a cover surface facing the stacked structure, a first fastening portion laterally protruding from a first side of the stacked structure in a stacking direction of the plurality of stacked battery cells, and a second fastening portion laterally protruding from a second side of the stacked structure in the stacking direction.
    Type: Application
    Filed: May 30, 2024
    Publication date: September 19, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Ji Woong Jung, Yong Hwan Choi, Yu Ri Oh, Tae Hyuck Kim, Gyung Hoon Shin, Hae Kyu Lim
  • Patent number: 12094924
    Abstract: A capacitor structure, a semiconductor memory device including the same, a method for fabricating the same, and a method for fabricating a semiconductor device including the same are provided. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric film which is interposed between the lower electrode and the upper electrode, wherein the lower electrode includes an electrode film including a first metal element, and a doping oxide film including an oxide of the first metal element between the electrode film and the capacitor dielectric film, and the doping oxide film further includes a second metal element including at least one of Group 5 to Group 11 and Group 15 metal elements, and an impurity element including at least one of silicon (Si), aluminum (Al), zirconium (Zr) and hafnium (Hf).
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: September 17, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoo Ho Jung, Sang Yeol Kang, Su Hwan Kim, Dong Kwan Baek, Yu Kyung Shin, Won Sik Choi
  • Publication number: 20240304826
    Abstract: A highly durable electrolyte membrane using cerium oxide supported with an alloy catalyst that is a hydrogen-oxygen reaction catalyst for improving chemical durability of an electrolyte membrane increases durability of a membrane-electrode assembly including the same and decreases the manufacturing cost thereof.
    Type: Application
    Filed: November 20, 2023
    Publication date: September 12, 2024
    Inventors: In Yu Park, Jong Kil Oh, Woo Chul Jung, Seung Hyun Kim, Dong Hwan Oh
  • Publication number: 20240242323
    Abstract: Disclosed is an apparatus for improving construction precision based on extended reality (XR). At least one piece of XR content related to a construction target positioned in front inside a construction site is displayed on a display unit. When a construction position of a construction object included in the construction target is determined, the XR content including the design information of the construction object at the construction position is displayed on the display unit.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Applicants: SLZ Inc.
    Inventors: Jae Heon JUNG, Yu Mi LEE, Tae Yang SHIN, Jeong Hwan LEE
  • Patent number: 7898880
    Abstract: A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: March 1, 2011
    Assignee: Mtekvision Co., Ltd.
    Inventors: Yu-Hwan Jung, Ji-Tae Ha, Chang-Hyuk Hui, Young-Hun Lim
  • Publication number: 20100232238
    Abstract: A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface).
    Type: Application
    Filed: September 12, 2007
    Publication date: September 16, 2010
    Inventors: Yu-Hwan Jung, Ji-Tae Ha, Chang-Hyuk Hui, Young-Hun Lim