Abstract: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

Abstract: A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage.

Abstract: A memory device is provided, which includes a plurality of global bit lines, a discharge line, a switching circuit configured to connect the plurality of global bit lines to the discharge line in response to a discharge enable signal, a first discharge circuit configured to apply a first voltage that is higher than a ground voltage to the discharge line, a precharge circuit configured to apply a precharge voltage to a selected global bit line among the plurality of global bit lines, and a second discharge circuit configured to discharge the selected global bit line to a second voltage that is higher than the ground voltage.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

Abstract: A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

Abstract: A resistance-variable memory device includes memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell may, for example, include a resistance-variable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline using the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage.

Abstract: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

Abstract: Provided is a method of testing a phase change random access memory (PRAM). The method may include providing a plurality of PRAM cells each coupled between each of a plurality of first lines and each of a plurality of second lines intersecting the first lines, selecting at least one of the plurality of first lines while deselecting the remaining first lines and the plurality of second lines, pre-charging the selected at least one of the plurality of first lines to a predetermined or given voltage level, and sensing a change in the voltage level of the selected first line while supplying a monitoring voltage to the selected first line.

Abstract: In various methods of performing program operations in phase change memory devices, selected memory cells are repeatedly programmed to obtain resistance distributions having desired characteristics such as adequate sensing margins.

Abstract: A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.

Abstract: Disclosed is a phase-changeable memory device and method of programming the same. The phase-changeable memory device includes memory cells each having multiple states, and a program pulse generator providing current pulses to the memory cells. The program pulse generator initializes a memory cell to a reset or set state by applying a first pulse thereto and thereafter provides a second pulse to program the memory cell to one of the multiple states. According to the invention, as a memory cell is programmed after being initialized to a reset or set state, it is possible to correctly program the memory cell without influence from the previous state of the memory cell.

Abstract: A nonvolatile memory device that utilizes both a voltage provided outside the memory device and a voltage generated within the device instead of using only a voltage generated within the device as a driving voltage avoids malfunctions of the memory device when instantaneous significant voltage drops occur. The nonvolatile memory device includes a plurality of nonvolatile memory cells, a bit line coupled to at least a portion of the plurality of nonvolatile memory cells, a column-selection transistor coupled to the bit line and a driving circuit. The driving circuit is coupled to a gate of the column-selection transistor and is configured to supply a charge to the gate using a first voltage and a second voltage wherein the second voltage is higher than the first voltage.

Abstract: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.