Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

Abstract: A device includes a substrate, a pull-down transistor over the substrate, a pass-gate transistor over the substrate, and a pull-up transistor over the substrate. The pull-up transistor includes a first gate structure and first source/drain epitaxy structures on opposite sides of the first gate structure, in which each of the first source/drain epitaxy structures comprises a first epitaxy layer and a second epitaxy layer over the first epitaxy layer, wherein a germanium concentration of the first epitaxy layer is higher than a germanium concentration of the second epitaxy layer.

Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

Abstract: A method includes forming a first semiconductor fin over a p-well region of a substrate; forming a second semiconductor fin over an n-well region of a substrate; forming a gate structure crossing the first semiconductor fin and the second semiconductor fin; performing an implantation process to form a source/drain doped region in the first semiconductor fin; etching the second semiconductor fin to form a recess therein; performing a first epitaxy process to grow a first epitaxy layer in the recess; performing a second epitaxy process to grow a second epitaxy layer over the first epitaxy process; etching the second epitaxy layer to round a corner of the second epitaxy layer; forming an interlayer dielectric (ILD) layer covering the first semiconductor fin and the second epitaxy layer, wherein no etching is performed to the first semiconductor fin after forming the gate structure and prior to forming the ILD layer.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a plurality of isolation structures adjacent to the semiconductor fin; etching the semiconductor fin to form a recess between the isolation structures; forming a first epitaxy layer in the recess; forming a second epitaxy layer over the first epitaxy layer; forming a third epitaxy layer over the second epitaxy layer, in which the first epitaxy layer has a higher germanium (Ge) concentration than the second and third epitaxy layers; etching the third epitaxy layer; and forming a dielectric layer in contact with the third epitaxy layer after etching the third epitaxy layer.