Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

Abstract: Abstract of Disclosure The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a transistor disposed on the substrate, wherein the transistor comprises a gate structure, a source and a drain, and the gate structure of the transistor located on the substrate and extending along a first direction, and a plurality of supporting patterns located in the gate structure of the transistor, wherein the plurality of supporting patterns are separated from each other and arranged along a second direction, wherein the second direction is perpendicular to the first direction, and wherein at least four supporting patterns of the plurality of supporting patterns constitute a supporting pattern dashed line, wherein the supporting pattern dashed line extends along the second direction.

Abstract: A semiconductor component is provided in the form of an enhancement mode high-electron-mobility transistor having an n-i-p semiconductor junction epitaxial structure. The semiconductor component includes: a channel layer and a barrier layer formed on the channel layer. A two-dimensional electron gas (2DEG) is formed in the channel layer adjacent to an interface between the channel layer and the barrier layer. A gate electrode is disposed on the barrier layer. A semiconductor junction structure is disposed and sandwiched between the gate electrode and the barrier layer. The semiconductor junction structure includes a first region doped with a first dopant and in direct contact with the gate electrode, a second region doped with a second dopant different from the first dopant, and a third region being unintentionally doped and sandwiched between the first region and the second region. The semiconductor junction structure depletes a portion of the 2DEG thereunder.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: Aspects of the disclosure relate to an automated iterative predictive modeling computing platform that iteratively requests additional data from external data sources to iteratively generate a more accurate insurance premium estimation. In some instances, the automated iterative predictive modeling computing platform may generate an insurance premium estimation using affordable insurance data and using estimated data in place of missing data. If the insurance premium estimation does not meet predefined confidence thresholds, the automated iterative predictive modeling computing platform may retrieve additional data that is more expensive but also has a likelihood to generate a more accurate insurance premium estimation. This process may be repeated using different data sets from different external data sources until a sufficiently accurate insurance premium estimate is generated by the automated iterative predictive modeling computing platform.

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a gate structure which extends along a first direction, and a plurality of supporting patterns which are separated from each other and arranged along a second direction which is perpendicular to the first direction.

Abstract: The invention provides a method for reducing mismatch of semiconductor device patterns, which comprises the following steps: defining an initial lithography area which partially overlaps a target gate structure, a first gate structure and a second gate structure; if a length and a width of the target gate structure are smaller than a preset channel length and a preset channel width respectively, adjusting and reducing the area of the initial lithography area to define a second lithography area. The second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography region is defined as the active area.

Abstract: The invention provides a method for reducing mismatch of semiconductor device patterns, which comprises the following steps: defining an initial lithography area which partially overlaps a target gate structure, a first gate structure and a second gate structure; if a length and a width of the target gate structure are smaller than a preset channel length and a preset channel width respectively, adjusting and reducing the area of the initial lithography area to define a second lithography area. The second lithography area partially overlaps with the target gate structure but does not overlap with the first gate structure and the second gate structure, and the second lithography region is defined as the active area.

Abstract: An electronic device includes a substrate, at least one electronic element and a heat dissipating electromagnetic shielding structure. The heat dissipating electromagnetic shielding structure is disposed on the substrate and covers the at least one electronic element, wherein the heat dissipating electromagnetic shielding structure includes a shielding frame and a heatsink. The shielding frame includes a plurality of spring members. The spring members are bent toward the substrate and partially abut against the heatsink. When the heatsink and the shielding frame are correspondingly arranged, a shielding space is defined, the electronic element is disposed in the shielding space, and a heat generated by the at least one electronic element is conducted out of the shielding space via the heatsink.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate; forming an inter-metal dielectric (IMD) layer on the metal gate; forming a metal interconnection in the IMD layer; and performing a high pressure anneal (HPA) process for improving work function variation of the metal gate.

Abstract: An example balancing structure includes a stand and a balancing structure. The stand is to support the object to stand on a plane, and adjust a position of the object. The balancing structure is installed on a base of the stand and is to balance a tipping force of the base suffered from an adjustment of the position of the object.

Abstract: An example balancing structure includes a stand and a balancing structure. The stand is to support the object to stand on a plane, and adjust a position of the object. The balancing structure is installed on a base of the stand and is to balance a tipping force of the base suffered from an adjustment of the position of the object.

Abstract: A mosquito trap device includes a housing having an air inlet and an air outlet. A wind channel is formed between the air inlet and the air outlet. An ultraviolet light module is mounted in the housing and is located adjacent to the air inlet. A wind module is mounted in the wind channel of the housing. A mosquito detaining device includes a tube and a net. The tube is mounted in the wind channel and is coupled to the wind module. The net is mounted to and covers an end of the tube adjacent to the air inlet. A controller is electrically connected to the ultraviolet light module and the wind module. The controller is configured to output a pulse width modulation signal to the ultraviolet light module. The pulse width modulation signal has a frequency of 25-512 Hz.

Abstract: A bug zapper includes a body, a fan and a light source. The body has a compartment, an opening, a channel arranged between the compartment and the opening, and a coupling portion arranged between the compartment and the channel. The channel is formed by an enclosed reflection wall and gradually expands from the coupling portion towards the opening. The fan is coupled with the coupling portion. The light source is mounted on a location of the body adjacent to the fan and irradiates light in the channel. As such, the efficiency in attracting the mosquitoes is outstanding, and the negative effect to the human is reduced.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

Abstract: A clustered energy-storing micro-grid system includes a renewable energy device, a clustered energy-storing device, an electrical power conversion device and a local controller. Before coordinating and allocating power to a plurality of loads, the clustered energy-storing device stores and releases the power in a centralized manner. This, coupled with the control exercised by the local controller over the electrical power conversion device, controls the micro-grid system in its entirety so that the micro-grid system operates in cost-efficient optimal conditions, under a predetermined system operation strategy, and in a system operation mode.

Abstract: A simulation test system of a cluster-based microgrid integrated with energy storages is characterized in that an operation simulation test of a physical microgrid system is conducted with a computer as well as a power generation data and a power consumption data which are imported. Hence, the user can verify the feasibility of applying various design concepts and ideas, such as controller parameter design and system energy management strategies, to a physical microgrid system, without installing or using any physical apparatuses.