Abstract: Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.

Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.

Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.