Patents by Inventor YU-JIA HUO
YU-JIA HUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10475936Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.Type: GrantFiled: November 17, 2017Date of Patent: November 12, 2019Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Jia Huo, Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
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Patent number: 10431662Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.Type: GrantFiled: November 20, 2017Date of Patent: October 1, 2019Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Jia Huo, Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
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Patent number: 10347854Abstract: The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.Type: GrantFiled: November 20, 2017Date of Patent: July 9, 2019Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
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Patent number: 10326089Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.Type: GrantFiled: November 20, 2017Date of Patent: June 18, 2019Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
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Publication number: 20180158921Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the first sub-dielectric layer. The thin film transistor almost has no current hysteresis.Type: ApplicationFiled: November 20, 2017Publication date: June 7, 2018Inventors: YU-JIA HUO, YU-DAN ZHAO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20180158960Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate on the substrate; a dielectric layer on the gate, wherein the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer formed by magnetron sputtering and in direct contact with the gate; a semiconductor layer on the dielectric layer, wherein the semiconductor layer includes nano-scaled semiconductor materials; and a source and a drain, wherein the source and the drain are on the dielectric layer, spaced apart from each other, and electrically connected to the semiconductor layer. The thin film transistor almost has no current hysteresis.Type: ApplicationFiled: November 17, 2017Publication date: June 7, 2018Inventors: YU-JIA HUO, YU-DAN ZHAO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20180159056Abstract: The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.Type: ApplicationFiled: November 20, 2017Publication date: June 7, 2018Inventors: YU-DAN ZHAO, YU-JIA HUO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20180158904Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a gate located on the substrate; a dielectric layer located on the gate; a semiconductor layer located on the dielectric layer and including nano-scaled semiconductor materials; and a drain and a source spaced apart from each other and electrically connected to the semiconductor layer. The dielectric layer is an oxide layer formed by magnetron sputtering and in direct contact with the gate. The thin film transistor has inverse current hysteresis.Type: ApplicationFiled: November 20, 2017Publication date: June 7, 2018Inventors: YU-DAN ZHAO, YU-JIA HUO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20180158905Abstract: The disclosure relates to a thin film transistor and a method for making the same. The thin film transistor includes a substrate; a semiconductor layer on the substrate, wherein the semiconductor layer includes nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer on the semiconductor layer, wherein the dielectric layer is an oxide dielectric layer formed by magnetron sputtering; and a gate in direct contact with the dielectric layer. The thin film transistor has inverse current hysteresis.Type: ApplicationFiled: November 20, 2017Publication date: June 7, 2018Inventors: YU-DAN ZHAO, YU-JIA HUO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN
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Publication number: 20180159057Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.Type: ApplicationFiled: November 20, 2017Publication date: June 7, 2018Inventors: YU-DAN ZHAO, YU-JIA HUO, XIAO-YANG XIAO, YING-CHENG WANG, TIAN-FU ZHANG, YUAN-HAO JIN, QUN-QING LI, SHOU-SHAN FAN