Patents by Inventor Yu-jin Seo

Yu-jin Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11812609
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Yu Jin Seo, Jun Eon Jin
  • Publication number: 20230174465
    Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.
    Type: Application
    Filed: April 27, 2021
    Publication date: June 8, 2023
    Inventors: Yong Tae KWON, Hyun Tae KIM, Jeong Eun NA, Yu Jin SEO, Chang Hoon JI, Ha Rim CHOI, Ji Eun LEE, Ah Jung HEO
  • Publication number: 20230174470
    Abstract: The present specification relates to a compound as a UBR box domain ligand. The present specification provides a small molecule compound that binds to the UBR box domain. Further, the present specification provides a composition for inhibiting UBR box domain substrate binding, including a ligand compound that binds to a UBR box domain, a pharmaceutical composition for treating UBR-related disease, and a use thereof.
    Type: Application
    Filed: April 27, 2021
    Publication date: June 8, 2023
    Inventors: Yong Tae KWON, Hyun Tae KIM, Jeong Eun NA, Yu Jin SEO, Chang Hoon JI, Ha Rim CHOI, Ji Eun LEE, Ah Jung HEO
  • Publication number: 20220032300
    Abstract: A multiplex PCR chip capable of simultaneously detecting multiple target genes and a multiplex PCR method using the same are proposed. More specifically, in the multiplex PCR chip and multiplex PCR method, after a plurality of spatially separated particle-forming grooves is formed in one or more reaction chambers and a probe in a solution state is injected into the particle-forming grooves, planar shapes of the particle-forming grooves are varied or shapes and patterns of particle holders respectively formed on inner surfaces of the particle-forming grooves are varied, and the probe including primers specifically hybridizing with sequences of different nucleic acid molecules is injected into the particle-forming grooves, whereby simultaneous multiplex detection is possible by allowing multiple target genes to be detected on the basis of positions and shapes of the probe particles and the shapes and patterns of the particle holders respectively formed inside of the probe particles.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 3, 2022
    Applicant: Genesystem Co., Ltd.
    Inventors: Yu Jin SEO, Ok Ran CHOI, Dobu LEE, Ji Young PARK
  • Publication number: 20210242229
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Application
    Filed: March 31, 2021
    Publication date: August 5, 2021
    Inventors: BYOUNG IL LEE, Yu Jin Seo, Jun Eon Jin
  • Patent number: 11004866
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung il Lee, Jun Ho Cha
  • Patent number: 10998327
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 4, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Su Bin Kang, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Patent number: 10978465
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung Il Lee, Yu Jin Seo, Jun Eon Jin
  • Publication number: 20200185412
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: TAK LEE, SU BIN KANG, JI MO GU, YU JIN SEO, BYOUNG iL LEE, JUN HO CHA
  • Patent number: 10566346
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Publication number: 20190355736
    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 21, 2019
    Inventors: SU BIN KANG, Byoung Il Lee, Ji Mo Gu, Yu Jin Seo, Tak Lee
  • Publication number: 20190355737
    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 21, 2019
    Inventors: BYOUNG IL LEE, YU JIN SEO, JUN EON JIN
  • Publication number: 20190244969
    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.
    Type: Application
    Filed: August 22, 2018
    Publication date: August 8, 2019
    Inventors: Tak Lee, Su Bin Kang, Ji Mo Gu, Yu Jin Seo, Byoung Il Lee, Jun Ho Cha
  • Publication number: 20180175143
    Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 21, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chan-sic YOON, Ki-seok Lee, Ki-wook Jung, Dong-oh Kim, Ho-in Lee, Je-min Park, Seok-han Park, Augustin Hong, Ju-yeon Jang, Hyeon-ok Jung, Yu-jin Seo
  • Patent number: 7892490
    Abstract: Provided is an apparatus for performing a chemical reaction using a microchip having at least one micro-channel. The device, which is a semiautomatic operating device for a microchip on which at least one micro-channel with a reagent inlet is formed, includes: a base which accommodates the microchip; a slider with injection inlets corresponding to the reagent inlets that reciprocally move parallel to the base; and a slider moving unit which selectively moves the slider to a first location at which the microchip is opened, after the injection inlet of the slider and the reagent inlet are aligned, and to a second location where the microchip is sealed by a bottom surface of the slider covering the reagent inlet.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: February 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-wook Oh, Yu-jin Seo
  • Patent number: 7754452
    Abstract: Provided are a polymerase chain reaction (PCR) module and a PCR system including the same. The PCR module includes: a detachable PCR chip including a PCR chamber unit in which a PCR solution is accommodated; a heater unit for heating the PCR solution in the PCR chip with a preset temperature; a detecting unit for detecting a PCR signal of the PCR solution; a PCR chip installation unit for mounting/detaching the PCR chip using a one-touch method, in which the heater unit is adhered to the PCR chip with a predetermined pressure when mounting the PCR chip and the heater unit is separated from the PCR chip when detaching the PCR chip; and a housing covering at least the heater unit and the detecting unit so that they are not exposed to the outside.
    Type: Grant
    Filed: March 16, 2006
    Date of Patent: July 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-tae Kim, Kak Namkoong, Kwang-wook Oh, Chin-sung Park, Yu-jin Seo
  • Patent number: 7413707
    Abstract: Provided is a microchip assembly including a base holder, a microchip installed on the base holder and having at least one input hole into which a reaction sample is input and at least one microchamber accommodating the input reaction sample, a flipper rotatably installed at the outside of the microchip on the base holder and opening and closing the input hole of the microchip while flipping up in a vertically erected state or flipping down in a horizontal state, and slider installed at the outside of the flipper on the base holder to be capable of sliding and supporting the flipper in the erected state and flipping down the flipper while moving inside.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang-wook Oh, Yu-jin Seo
  • Publication number: 20060286582
    Abstract: Provided is a microchip assembly including a base holder, a microchip installed on the base holder and having at least one input hole into which a reaction sample is input and at least one microchamber accommodating the input reaction sample, a flipper rotatably installed at the outside of the microchip on the base holder and opening and closing the input hole of the microchip while flipping up in a vertically erected state or flipping down in a horizontal state, and slider installed at the outside of the flipper on the base holder to be capable of sliding and supporting the flipper in the erected state and flipping down the flipper while moving inside.
    Type: Application
    Filed: May 9, 2006
    Publication date: December 21, 2006
    Inventors: Kwang-wook Oh, Yu-jin Seo
  • Publication number: 20060246487
    Abstract: Provided is an apparatus for performing a chemical reaction using a microchip having at least one micro-channel. The device, which is a semiautomatic operating device for a microchip on which at least one micro-channel with a reagent inlet is formed, includes: a base which accommodates the microchip; a slider with injection inlets corresponding to the reagent inlets that reciprocally move parallel to the base; and a slider moving unit which selectively moves the slider to a first location at which the microchip is opened, after the injection inlet of the slider and the reagent inlet are aligned, and to a second location where the microchip is sealed by a bottom surface of the slider covering the reagent inlet.
    Type: Application
    Filed: March 29, 2006
    Publication date: November 2, 2006
    Inventors: Kwang-wook Oh, Yu-jin Seo
  • Publication number: 20060246580
    Abstract: Provided are a polymerase chain reaction (PCR) module and a PCR system including the same. The PCR module includes: a detachable PCR chip including a PCR chamber unit in which a PCR solution is accommodated; a heater unit for heating the PCR solution in the PCR chip with a preset temperature; a detecting unit for detecting a PCR signal of the PCR solution; a PCR chip installation unit for mounting/detaching the PCR chip using a one-touch method, in which the heater unit is adhered to the PCR chip with a predetermined pressure when mounting the PCR chip and the heater unit is separated from the PCR chip when detaching the PCR chip; and a housing covering at least the heater unit and the detecting unit so that they are not exposed to the outside.
    Type: Application
    Filed: March 16, 2006
    Publication date: November 2, 2006
    Inventors: Jin-tae Kim, Kak Namkoong, Kwang-wook Oh, Chi-sung Park, Yu-jin Seo