Patents by Inventor Yu-Jing Lin

Yu-Jing Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11959956
    Abstract: A circuit check method and an electronic apparatus applicable to a to-be-tested circuit are provided. The to-be-tested circuit has one or more first nodes related to a gate voltage of one or more transistor devices and a plurality of second nodes. The circuit check method includes: setting endpoint voltages of a plurality of input interface ports of the to-be-tested circuit; obtaining a first node voltage of the first node according to a conduction path of the to-be-tested circuit and the gate voltage of the transistor device; obtaining a second node voltage of each second node according to the conduction path, the endpoint voltages, and the first node voltage; and performing circuit static check on the to-be-tested circuit by applying the first node voltage and the second node voltage.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: April 16, 2024
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yun-Jing Lin, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Publication number: 20120298329
    Abstract: An air flow adjusting frame for a heat sink device which includes a first fixing plate and a second fixing plate is disclosed. The first fixing plate is fixed to a heat dissipation fin with the second fixing plate pivoted to the first fixing plate. Besides, the second fixing plate is for being fixed to a fan. An air flow angle of the fan is adjusted through the air flow adjusting frame.
    Type: Application
    Filed: August 31, 2011
    Publication date: November 29, 2012
    Applicant: MICRO-STAR INT'L CO., LTD.
    Inventors: Yi-Chieh Lin, Yu-Jing Lin
  • Patent number: 6181390
    Abstract: A liquid crystal computer display structure including a liquid crystal display panel two sides of which are respectively locked with two fixing plates. At least one supporting plate is locked with the fixing plates. A liquid crystal display circuit board is locked on the supporting plate. Each side of the display panel is fitted with a side frame. The side frames are structurally identical to each other, while having different lengths. A metal back cover is disposed on back side of the display circuit board for reducing electromagnetic interference.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: January 30, 2001
    Assignee: Compal Electronics, Inc.
    Inventors: Ping-Hsien Wang, Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D398911
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: September 29, 1998
    Assignee: Compal Electronics, Inc.
    Inventor: Yu-Jing Lin
  • Patent number: D409167
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: May 4, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D409587
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: May 11, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D411522
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: June 29, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D415130
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: October 12, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D415478
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: October 19, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D416875
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: November 23, 1999
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin
  • Patent number: D422576
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: April 11, 2000
    Assignee: Compal Electronics, Inc.
    Inventors: Yu-Hsin Chuo, Yu-Jing Lin