Patents by Inventor Yu-Jiun PENG
Yu-Jiun PENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420567Abstract: A method for forming a multi-gate semiconductor structure is provided. A substrate including a fin structure is received. First portions of the fin structure are removed to expose a source/drain region of the fin structure. A semiconductor layer is formed in the source/drain region. Second portions of the fin structure are removed to expose a channel region of the fin structure. A surface of the channel region of the fin structure is cleaned. An interfacial layer is formed over the cleaned surface of the channel region of the fin structure.Type: ApplicationFiled: June 26, 2022Publication date: December 28, 2023Inventors: CHUN-MING YANG, YU-JIUN PENG, YU-WEN WANG
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Publication number: 20230187288Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Chang-Jhih Syu, Chih-Hao Yu, Chang-Yun Chang, Hsiu-Hao Tsao, Yu-Jiun Peng
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Publication number: 20230187535Abstract: Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a fin structure protruding from a substrate, and the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method also includes forming a dummy gate structure across the fin structure and forming a gate spacer on a sidewall of the dummy gate structure. The method also includes partially oxidizing the gate spacer to form an oxide layer and removing the oxide layer to form a modified gate spacer. The method also includes removing the first semiconductor material layers to form gaps and forming a gate structure in the gaps to wrap around the second semiconductor material layers and over the second semiconductor material layers to cover the modified gate spacer.Type: ApplicationFiled: June 2, 2022Publication date: June 15, 2023Inventors: Yu-Jiun Peng, Hsuan-Chih Wu, Cheng-Chung Chang, Shu-Han Chen, Hsiu-Hao Tsao, Min-Chia Lee, Kai-Min Chien, Ming-Chang Wen, Kuo-Feng Yu, Chang-Jhih Syu
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Patent number: 11574846Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.Type: GrantFiled: October 20, 2020Date of Patent: February 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chang-Jhih Syu, Chih-Hao Yu, Chang-Yun Chang, Hsiu-Hao Tsao, Yu-Jiun Peng
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Publication number: 20220351975Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: ApplicationFiled: July 12, 2022Publication date: November 3, 2022Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
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Publication number: 20220336639Abstract: A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.Type: ApplicationFiled: September 2, 2021Publication date: October 20, 2022Inventors: Chien-Chih LIN, Hsiu-Hao TSAO, Szu-Chi YANG, Shih-Hao LIN, Yu-Jiun PENG, Chang-Jhih SYU, An Chyi WEI
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Patent number: 11398384Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: GrantFiled: February 11, 2020Date of Patent: July 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
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Publication number: 20210249271Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Inventors: Yu-Jiun Peng, Hsiu-Hao Tsao, Shu-Han Chen, Chang-Jhih Syu, Kuo-Feng Yu, Jian-Hao Chen, Chih-Hao Yu, Chang-Yun Chang
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Publication number: 20210183713Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.Type: ApplicationFiled: October 20, 2020Publication date: June 17, 2021Inventors: Chang-Jhih Syu, Chih-Hao Yu, Chang-Yun Chang, Hsiu-Hao Tsao, Yu-Jiun Peng
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Patent number: 11031470Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.Type: GrantFiled: January 9, 2020Date of Patent: June 8, 2021Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
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Publication number: 20200144368Abstract: A semiconductor device includes a substrate, a channel structure and a metal gate structure. The channel structure protrudes above the substrate. The channel structure includes alternately stacked first portions and second portions having widths greater than widths of the first portions, and the first portions and the second portions are made of the same semiconductor material. The metal gate structure wraps around the channel structure.Type: ApplicationFiled: January 9, 2020Publication date: May 7, 2020Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU
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Patent number: 10535737Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.Type: GrantFiled: October 27, 2017Date of Patent: January 14, 2020Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITYInventors: Fang-Liang Lu, Chia-Che Chung, Yu-Jiun Peng, Chee-Wee Liu
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Publication number: 20190131403Abstract: A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Inventors: Fang-Liang LU, Chia-Che CHUNG, Yu-Jiun PENG, Chee-Wee LIU