Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit is configured to perform a program operation on the memory cell array. The control logic is configured to control the program operation performed by the peripheral circuit. Each of the plurality of memory blocks is coupled to a drain select line, a plurality of word lines, and first and second source select lines that correspond to the memory block. During a program operation performed on a first memory block selected as a program target, among the plurality of memory blocks, the control logic controls the peripheral circuit so that a first source select line of a second memory block that is not selected as the program target, among the plurality of memory blocks, floats.

Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory blocks. The peripheral circuit is configured to perform a program operation on the memory cell array. The control logic is configured to control the program operation performed by the peripheral circuit. Each of the plurality of memory blocks is coupled to a drain select line, a plurality of word lines, and first and second source select lines that correspond to the memory block. During a program operation performed on a first memory block selected as a program target, among the plurality of memory blocks, the control logic controls the peripheral circuit so that a first source select line of a second memory block that is not selected as the program target, among the plurality of memory blocks, floats.

Abstract: The initialization signal generation circuit includes a first driver and a second driver. The first driver includes at least one passive element and drives an initialization signal while a level of an external voltage signal reaches an initial level. The second driver drives the initialization signal in response to a control signal from a point of time that a level of the external voltage signal reaches the initial level.

Abstract: The initialization signal generation circuit includes a first driver and a second driver. The first driver includes at least one passive element and drives an initialization signal while a level of an external voltage signal reaches an initial level. The second driver drives the initialization signal in response to a control signal from a point of time that a level of the external voltage signal reaches the initial level.

Abstract: A voltage generator includes a high voltage generator configured to include a plurality of pump circuits for generating various levels of a high voltage in response to clock signals, wherein the plurality of pump circuits are configured to receive enable signals corresponding to a level of voltage to be generated, where the enable signals are generated in response to internal operation signals. And a clock transfer circuit configured to generate a clock enable signal by comparing the high voltage and a reference voltage and to selectively provide the clock signals to each of the pump circuits in response to the clock enable signal and each of the enable signals.

Abstract: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first voltage, and a voltage of a global source line when a read or verification operation is performed on the nonvolatile memory device, and to output a changed first voltage as a second voltage, a second reference voltage generation unit configured to generate a second reference voltage, and an amplification unit configured to amplify a difference between the second voltage and the second reference voltage according to a set resistance ratio and to output a result of the amplification as a third voltage.

Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.

Abstract: An internal voltage generation circuit includes a pumping voltage generator including a plurality of pump units and configured to generate a final pumping voltage of a target voltage level, and an activation controller configured to control the number of activated pump units among the pump units based on the target voltage level.

Abstract: A voltage generator includes a high voltage generator configured to include a plurality of pump circuits for generating various levels of a high voltage in response to clock signals, wherein the plurality of pump circuits are configured to receive enable signals corresponding to a level of voltage to be generated, where the enable signals are generated in response to internal operation signals. And a clock transfer circuit configured to generate a clock enable signal by comparing the high voltage and a reference voltage and to selectively provide the clock signals to each of the pump circuits in response to the clock enable signal and each of the enable signals.

Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.

Abstract: An OP-amp circuit includes a first circuit unit configured to generate an operating voltage in response to an enable signal, a second circuit unit configured to amplify a difference between respective voltages received through an inverting terminal and a non-inverting terminal in response to the operating voltage and to output a result of the amplification as a first drive voltage, a third circuit unit configured to output a second drive voltage according to a voltage level of the first drive voltage inputted thereto, and a fourth circuit unit configured to divide an input voltage inputted thereto into a divided voltage according to two resistances having respective resistive values varying according to the first and second drive voltages and to output the divided voltage through an output terminal.

Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.

Abstract: A nonvolatile memory device includes a bit line sensing signal supply unit configured to output a bit line sensing signal, having a rising voltage level that rises in discrete steps, in response to a control signal, and a bit line sensing unit configured to selectively connect a bit line and a sensing node in response to the bit line sensing signal.

Abstract: A voltage generation circuit for providing a read or verification voltage of a nonvolatile memory device includes a first voltage generation unit configured to output a first voltage using a first reference voltage, a bouncing compensation unit configured to change the first voltage using a first control signal, the first voltage, and a voltage of a global source line when a read or verification operation is performed on the nonvolatile memory device, and to output a changed first voltage as a second voltage, a second reference voltage generation unit configured to generate a second reference voltage, and an amplification unit configured to amplify a difference between the second voltage and the second reference voltage according to a set resistance ratio and to output a result of the amplification as a third voltage.

Abstract: A page buffer includes a first ground voltage supply unit for applying a ground voltage to first and second registers according to a level of a sense node, and a second ground voltage supply unit for applying the ground voltage to the first and second registers irrespective of a level of the sense node. A method of programming a non-volatile memory device includes storing a high-level data in a first node of a first register of a plurality of page buffers, precharging a sense node with a high level, resetting the data stored in the first node of the first register according to a voltage level of the sense node, precharging the sense node with a high level, storing external data in the first node according to a voltage level of the sense node, and performing a program operation according to the data stored in the first node.

Abstract: An OP-amp circuit includes a first circuit unit configured to generate an operating voltage in response to an enable signal, a second circuit unit configured to amplify a difference between respective voltages received through an inverting terminal and a non-inverting terminal in response to the operating voltage and to output a result of the amplification as a first drive voltage, a third circuit unit configured to output a second drive voltage according to a voltage level of the first drive voltage inputted thereto, and a fourth circuit unit configured to divide an input voltage inputted thereto into a divided voltage according to two resistances having respective resistive values varying according to the first and second drive voltages and to output the divided voltage through an output terminal.

Abstract: A nonvolatile memory device includes a bit line sensing signal supply unit configured to output a bit line sensing signal, having a rising voltage level that rises in discrete steps, in response to a control signal, and a bit line sensing unit configured to selectively connect a bit line and a sensing node in response to the bit line sensing signal.

Abstract: An apparatus for generating a voltage includes a first voltage outputting circuit configured to receive an input voltage and adjust and output a first voltage in accordance with a temperature, a buffer circuit configured to receive the first voltage and output the received first voltage as a second voltage at an output node of the buffer circuit, and a second voltage outputting circuit configured to receive the second voltage at an input terminal and output a third voltage by dividing a driving voltage in accordance with a resistance ratio, wherein the second voltage outputting circuit includes a sub-voltage outputting circuit and a controlling circuit configured to adjust a voltage level of the third voltage through a feedback of the third voltage to the input terminal.

Abstract: A verification reference voltage supply unit includes a reference voltage supply unit, a temperature-dependent voltage supply unit, and an amplification unit. The reference voltage supply unit is configured to supply a first reference voltage and a second reference voltage, each of which is configured to maintain a constant value irrespective of a temperature variation. The temperature-dependent voltage supply unit is configured to receive the first reference voltage and generate a temperature-dependent voltage having a voltage level that increases in proportion to a temperature increase. The amplification unit is configured to amplify the temperature-dependent voltage and the second reference voltage and generate a verification reference voltage.

Abstract: A method of programming a flash memory device includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, and verifying whether the first memory cell is programmed through a first verifying voltage. The first program voltage that is repeatedly increased by a step voltage when the first memory cell is not programmed. A second memory cell coupled to an odd bit line is programmed by applying the first program voltage to the word line. Whether the second memory cell is programmed is verified using a second verifying voltage that is higher than the first verifying voltage. The second memory cell is programmed using a program voltage that is repeatedly increased by the step voltage when the second memory cell is not programmed.