Abstract: A polymer, a composition, and a polysiloxane-polyimide material thereof are provided. The polymer includes a first repeat unit and a second repeat unit. The first repeat unit has a structure represented by Formula (I) and the second repeat unit has a structure represented by Formula (II) wherein A1 and A3 are independently tetravalent moiety; A2 is a divalent moiety; n?1; m?1; R1 is independently hydrogen, C1-8 alkyl, C1-8 fluoroalkyl, C1-8 alkoxy, or C6-12 aryl; and R2 is independently hydrogen, C1-8 alkyl, C1-8 fluoroalkyl, C1-8 alkoxy, C6-12 aryl, or a reactive functional group.

Abstract: A polymer, a composition, and a polysiloxane-polyimide material thereof are provided. The polymer includes a first repeat unit and a second repeat unit. The first repeat unit has a structure represented by Formula (I) and the second repeat unit has a structure represented by Formula (II) wherein A1 and A3 are independently tetravalent moiety; A2 is a divalent moiety; n?1; m?1; R1 is independently hydrogen, C1-8 alkyl, C1-8 fluoroalkyl, C1-8 alkoxy, or C6-12 aryl; and R2 is independently hydrogen, C1-8 alkyl, C1-8 fluoroalkyl, C1-8 alkoxy, C6-12 aryl, or a reactive functional group.

Abstract: Disclosed herein are disintegrin variants, and methods for suppressing or inhibiting platelet aggregation in a subject in need thereof. The method includes administering to the subject in need thereof an effective amount of the present disintegrin variant to alleviate or ameliorate symptoms associated with diseases, disorders, and/or conditions resulted from platelet aggregation. According to preferred embodiments, the present disintegrin variant is applied as a coating on an implantable device, such as a stent or a catheter.

Abstract: A polyimide precursor solution is provided. The polyimide precursor solution includes 100 parts by weight of a fully aromatic polyamic acid, from 5 to 20 parts by weight of silica particles, from 5 to 80 parts by weight of an alkoxysilane, and from 40 to 80 parts by weight of a solvent.

Abstract: Disclosed herein are disintegrin variants, and methods for suppressing or inhibiting platelet aggregation in a subject in need thereof. The method includes administering to the subject in need thereof an effective amount of the present disintegrin variant to alleviate or ameliorate symptoms associated with diseases, disorders, and/or conditions resulted from platelet aggregation. According to preferred embodiments, the present disintegrin variant is applied as a coating on an implantable device, such as a stent or a catheter.

Abstract: A polyimide precursor solution is provided. The polyimide precursor solution includes 100 parts by weight of a fully aromatic polyamic acid, from 5 to 20 parts by weight of silica particles, from 5 to 80 parts by weight of an alkoxysilane, and from 40 to 80 parts by weight of a solvent.

Abstract: A polyimide precursor solution is provided. The polyimide precursor solution includes 100 parts by weight of a fully aromatic polyamic acid, 5-20 parts by weight of silica particles, 10-40 parts by weight of an alkoxysilane, and 60-80 parts by weight of a solvent.

Abstract: A flexible substrate embedded with wires includes a flexible substrate constituted by a polymer material, and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. A method for fabricating a flexible substrate embedded with wires providing a carrier; forming a continuous wire pattern on the carrier, the continuous wire pattern containing a plurality of pores; covering a polymer material over the continuous wire pattern and the carrier and to fill into the pores; and separating the polymer material and the carrier to form a flexible substrate embedded with the continuous wire pattern” where the only change is the addition of wires.

Abstract: Disclosed is a substrate structure for manufacturing a flexible electronic device, including a supporting layer, a release layer covering the supporting layer with a first area, wherein the release layer is an aromatic polyimide, and a flexible layer covering the supporting layer and the release layer with a second area. The second area is greater than the first area. The adhesion force between the flexible layer and the supporting layer is stronger than the adhesion force between the release layer and the supporting layer.

Abstract: A flexible substrate embedded with wires is provided. The flexible substrate embedded with wires includes a flexible substrate constituted by a polymer material, and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. A method for fabricating a flexible substrate embedded with wires is also provided.

Abstract: Disclosed is a substrate structure for manufacturing a flexible electronic device, including a supporting layer, a release layer covering the supporting layer with a first area, wherein the release layer is an aromatic polyimide, and a flexible layer covering the supporting layer and the release layer with a second area. The second area is greater than the first area. The adhesion force between the flexible layer and the supporting layer is stronger than the adhesion force between the release layer and the supporting layer.

Abstract: A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal.

Abstract: A shift register unit includes a plurality of register units electrically coupled in cascade. Each register unit outputs an output pulse according to a first clock signal, a second clock signal and an output pulse of a previous register unit. Each register unit includes a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, and a driving unit. The first switch unit is used for conducting the input pulse to a first node when the first switch is turned on. The second switch unit is used for conducting the output pulse of the register unit according to the first clock signal to an output end when the second switch unit is turned on in response to the input pulse. The third switch unit electrically coupled to a supply end is used for conducting a supply voltage to the output end when the second switch unit is turned off.

Abstract: A signal-driving system for constructing gate signals of liquid crystal display (LCD), includes a plural stage of cascaded shift register units. Each stage of shift register unit includes a first pull-up switch unit, which is turned on for outputting a gate pulse on an output of this stage, based on either the first clock signal or the second clock signal; a pull-up driving unit, which is used for providing a driving pulse via a node for driving the first pull-up switch unit; a first pull-down switch unit, which is turned on to connect the output to a low-level voltage source; a second pull-down switch unit, which is turned on to connect said node to the low-level voltage source; a carry buffer unit, which is used for providing a control pulse on the second pull-down switch unit of previous stage, based on either the first clock signal or the second clock signal, and thereby ensuring operation of each stage independent of gate pulse signals outputted from the other stages.

Abstract: A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal.

Abstract: A driving circuit unit outputting a driving signal includes an input unit, an assistant output unit and an output unit. The input unit is coupled to an input node and receives a start signal to make the input node have a potential. The assistant output unit receives a first clock signal to increase the potential of the input node. The output unit receives a second clock signal to increase the potential of the input node and outputs the driving signal. A gate driving circuit is also disclosed.

Abstract: A display apparatus comprises a shift register array. The shift register array comprises a plurality of shift registers. At least one shift register comprises a first transistor, a second transistor, a third transistor, and a driving circuit. The gate and the first electrode of the first transistor receive an input signal. The gate of the second transistor is coupled to the second electrode of the first transistor. The second electrode of the second transistor generates an output signal. The first electrode of the second transistor receives a clock signal. The third transistor is used to pull down a voltage level at the gate of the second transistor. The driving circuit determines an on/off status of the third transistor in response to the input signal and the output signal.

Abstract: A gate driving circuit for driving plural scan lines of a liquid crystal display includes N driving circuit units and a control unit. Each of the N driving circuit units sequentially outputs a driving signal to drive a corresponding scan line of the scan lines. The control unit outputs a positive-phase and an opposite-phase clock signal to control the N driving circuit units. After an Nth driving circuit unit of the N driving circuit units outputs the driving signal, the control unit transmits a control signal to at least one of the N driving circuit units. A method for driving the foregoing gate driving circuit is also disclosed.

Abstract: A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.

Abstract: A shift register array is provided. The shift register array includes a plurality of shift registers connected in serial. The shift register includes a first transistor coupled between a first input terminal and a first node, a second transistor coupled between a first clock input terminal and an output terminal and a pull-up unit. The first transistor has a gate coupled to the first input terminal. The second transistor has a gate coupled to the first node. The pull-up unit includes a third transistor coupled between the first node and a ground, a capacitor coupled between the first clock input terminal and the second node and a fourth transistor coupled between the second node and the ground. The third transistor has a gate coupled to a second node. The fourth transistor has a gate coupled to the first node.