Patents by Inventor Yu-Ju LIAO
Yu-Ju LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145380Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
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Patent number: 11972975Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.Type: GrantFiled: June 24, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
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Patent number: 11953372Abstract: An optical sensing device is disclosed. The optical sensing device includes a sensing pixel, a driving circuit and a first light shielding layer. The sensing pixel includes a sensing circuit and a sensing element electrically connected to the sensing circuit. The driving circuit is electrically connected to the sensing circuit. The first light shielding layer includes at least one first opening corresponding to the sensing element, and the first light shielding layer is overlapped with the driving circuit in a top-view direction of the optical sensing device.Type: GrantFiled: January 18, 2022Date of Patent: April 9, 2024Assignee: InnoLux CorporationInventors: Yu-Tsung Liu, Wei-Ju Liao, Wei-Lin Wan, Cheng-Hsueh Hsieh, Po-Hsin Lin, Te-Yu Lee
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Patent number: 11942364Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.Type: GrantFiled: July 20, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
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Publication number: 20240088022Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
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Patent number: 11923293Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.Type: GrantFiled: July 8, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
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Patent number: 11848280Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.Type: GrantFiled: November 25, 2020Date of Patent: December 19, 2023Assignee: ADVANCED SEMlCONDUCTOR ENGINEERING, INC.Inventors: Wen Hung Huang, Yu-Ju Liao
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Patent number: 11587881Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.Type: GrantFiled: March 9, 2020Date of Patent: February 21, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao, Chu-Jie Yang, Sheng-Hung Shih
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Publication number: 20220278052Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: ApplicationFiled: May 17, 2022Publication date: September 1, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO
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Publication number: 20220165683Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.Type: ApplicationFiled: November 25, 2020Publication date: May 26, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Wen Hung HUANG, Yu-Ju LIAO
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Patent number: 11335646Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: GrantFiled: March 10, 2020Date of Patent: May 17, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao
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Patent number: 11296030Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.Type: GrantFiled: April 29, 2019Date of Patent: April 5, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
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Embedded component package structure, embedded type panel substrate and manufacturing method thereof
Patent number: 11277917Abstract: An embedded component package structure including a circuit substrate, an embedded component and a stress compensation layer is provided. The circuit substrate includes a core layer and an asymmetric circuit structure, and the core layer has a first thickness. The embedded component is disposed in the core layer. The stress compensation layer is disposed on one side of the core layer, and the stress compensation layer has a second thickness between 4 ?m and 351 ?m.Type: GrantFiled: March 12, 2019Date of Patent: March 15, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang, I-Chia Lin -
Patent number: 11139179Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.Type: GrantFiled: September 9, 2019Date of Patent: October 5, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Fan Chen, Yu-Ju Liao
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Publication number: 20210287997Abstract: The present disclosure provides a substrate structure. The substrate structure includes an interconnection structure, a dielectric layer on the interconnection structure, an electronic component embedded in the dielectric layer, and a first conductive via penetrating through the dielectric layer and disposed adjacent to the electronic component. The interconnection structure includes a carrier having a first surface and a second surface opposite to the first surface, a first conductive layer disposed on the first surface of the carrier, and a second conductive layer disposed on the second surface of the carrier. The first conductive via and at least one of the first conductive layer and the second conductive layer define a first shielding structure surrounding the electronic component. A method of manufacturing a substrate structure is also disclosed.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO
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Publication number: 20210280521Abstract: A substrate structure is disclosed. The substrate structure includes a carrier, a dielectric layer on the carrier, a patterned organic core layer in the dielectric layer, and a conductive via. The patterned organic core layer defines a passage extending in the dielectric layer towards the carrier. The conductive via extends through the passage towards the carrier without contacting the patterned organic core layer.Type: ApplicationFiled: March 9, 2020Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Fan CHEN, Yu-Ju LIAO, Chu-Jie YANG, Sheng-Hung SHIH
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Patent number: 10950551Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.Type: GrantFiled: April 29, 2019Date of Patent: March 16, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yu-Ju Liao, Chien-Fan Chen, Chien-Hao Wang
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Publication number: 20210074554Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip.Type: ApplicationFiled: September 9, 2019Publication date: March 11, 2021Inventors: Chien-Fan CHEN, Yu-Ju LIAO
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Publication number: 20200343187Abstract: An embedded component package structure including a dielectric structure, a semiconductor chip, a first polymer layer, and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure. The first polymer layer covers the semiconductor chip and has a first thickness, and the first thickness is greater than a second thickness of the dielectric structure above the first polymer layer. The patterned conductive layer covers an upper surface of the dielectric structure and extends over the first polymer layer, and the patterned conductive layer is electrically connected to the semiconductor chip.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG
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Publication number: 20200343188Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.Type: ApplicationFiled: April 29, 2019Publication date: October 29, 2020Inventors: Yu-Ju LIAO, Chien-Fan CHEN, Chien-Hao WANG