Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present disclosure provides a reaction cassette for biochemical test. The reaction cassette includes a structural wall, a first flow guiding member and an obstacle member. The structural wall defines a reaction region and a channel region, wherein the reaction region is connected to the channel region. The first flow guiding member is disposed in the channel region, and a first angle between the structural wall and the first flow guiding member ranges between 0 and 60 degrees. The obstacle member is disposed on the structural wall, and a second angle between the obstacle member and the structural wall is greater than 90 degrees. The present disclosure further provides an assay device including said reaction assay for biochemical test.

Abstract: The present disclosure provides a reaction cassette for biochemical test. The reaction cassette includes a structural wall, a first flow guiding member and an obstacle member. The structural wall defines a reaction region and a channel region, wherein the reaction region is connected to the channel region. The first flow guiding member is disposed in the channel region, and a first angle between the structural wall and the first flow guiding member ranges between 0 and 60 degrees. The obstacle member is disposed on the structural wall, and a second angle between the obstacle member and the structural wall is greater than 90 degrees. The present disclosure further provides an assay device including said reaction assay for biochemical test.