Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light reflective region that adjoins the light trapping region and that is able to reflect light. The light trapping region is formed with a plurality of gaps and has a plurality of metal members. Adjacent ones of the metal members are separated by the gaps. Each of the gaps is configured with a width in such a manner that most light irradiating the light trapping region will pass through the gaps and be trapped in the chip body so as to form brightness contrast between the light trapping region and the light reflective region.

Abstract: A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light reflective region that adjoins the light trapping region and that is able to reflect light. The light trapping region is formed with a plurality of gaps and has a plurality of metal members. Adjacent ones of the metal members are separated by the gaps. Each of the gaps is configured with a width in such a manner that most light irradiating the light trapping region will pass through the gaps and be trapped in the chip body so as to form brightness contrast between the light trapping region and the light reflective region.

Abstract: A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Abstract: A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Abstract: A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Abstract: The invention relates to a layout method for a transistor with improved ESD robustness. The layout method includes defining a ring region from a first conductive type; defining a first and a second rectangular diffusion regions from a second conductive type, wherein the first and second rectangular diffusion regions are isolated from each other; defining a ring diffusion region of the second conductive type between the first and second rectangular diffusion regions; defining a first gate electrode between the first rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive region; and defining a second gate electrode between the second rectangular diffusion region of the second conductive type and the ring diffusion region of the second conductive type.

Abstract: A method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory is disclosed. Firstly, a substrate having a gate, a bit line and a source/drain region is provided and a insulating layer is formed on the substrate. Then, a dielectric layer is deposited on the insulating layer. Moreover, a contact hole is formed by defining and etching the dielectric layer and the insulating layer to expose a portion of the source/drain region. Furthermore, a conductive layer is deposited on the dielectric layer and the contact hole, wherein the etching selectivity ratio of the conductive layer is near the etching selectivity ratio of the dielectric layer. Finally, an electrode of the capacitor is formed by defining and etching the conductive layer, whereby the dielectric layer protects the portion of the electrode that is beneath the dielectric layer from being etched when misalignment occurs.

Abstract: The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.

Abstract: The present invention provides a dynamic random access memory structure comprises a semiconductor substrate; semiconductor devices on the substrate, a first dielectric layer on the substrate and the semiconductor devices, and bit lines on the first dielectric layer. The bit lines are connected to bit line contact structures in the first dielectric layer. Further, a second dielectric layer is on the first dielectric layer and the bit lines. The second dielectric layer has at least a wall structure thereon and a capacitor node is in the second dielectric layer and the first dielectric layer. The capacitor node has a bottom part connected to the semiconductor substrate and a side-wall of a top part adjacent to the wall structure.

Abstract: The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.

Abstract: A method, apparatus, article of manufacture, and a memory structure for monitoring and raising alerts in data processing jobs. The alert and monitoring system uses a monitor request table stored in a relational database as a central repository in which data process jobs insert monitoring requests. The monitoring requests specify the time at which alerts or monitoring notices should be taken, and if the data processing job fails to submit an updated monitor request, the action described in the monitor request is taken. Provision is made for customized actions to be taken via a action alert table, which stores additional data allowing conditional and logical invocation of actions.