Abstract: A triggerable circuitry for a Physically Unclonable Function (PUF) source and true random number generator comprises an array of metastable latches PUF cells units that produce output states in racing configuration dependent on manufacturing variations and noise fed into a counting circuit. The technology as a single circuit extracts detected random bits' states for true random numbers generation, different each time when requested, and is able to feed a PUF recovery system that will use the fairly static bits' patterns of the measured circuit although each time different.

Abstract: A triggerable circuitry for a Physically Unclonable Function (PUF) source and true random number generator comprises an array of metastable latches PUF cells units that produce output states in racing configuration dependent on manufacturing variations and noise fed into a counting circuit. The technology as a single circuit extracts detected random bits' states for true random numbers generation, different each time when requested, and is able to feed a PUF recovery system that will use the fairly static bits' patterns of the measured circuit although each time different.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: The present invention provides a chip ESD protection circuit, includes an integrated circuit layer and a conductive layer. A first ground bonding pad that is connected to a first ground wire of a first power domain is disposed on each of the first power domain and a second power domain in the integrated circuit layer. The first ground bonding pads are bonded to the conductive layer. A second power clamping unit is disposed on the second power domain. A first end of the second power clamping unit is connected to a second power wire of the second power domain, and a second end thereof is connected to the first ground wire or a second ground wire of the second power domain. According to the chip ESD protection circuit, the ESD protection capability of a chip can be improved. The occupied area of the chip is reduced.

Abstract: The present invention relates to a hot bar soldering method for soldering two circuit boards, including following steps: firstly, providing a first circuit board (4) including a plurality of first pads (42) and a second circuit board (5) including a plurality of second pads (52), each of the pads having opposite first and second ends, and the first pads being longer than the second pads; secondly, aligning each of the first pads and the corresponding second pads, and leaving the first ends (421) of the first pads uncovered by the second circuit board; finally, hot pressing the second circuit board where the first pads and the second pads overlap and simultaneously at the second ends of the first pads.