Abstract: A localization device and a localization method for a vehicle are provided. The localization device includes an inertia measurer, an encoder, an image capturing device, and a processor. The processor obtains an encoded data by the encoder to generate a first odometer data, obtains an inertial data by the inertia measurer to generate a heading angle estimation data, and obtains an environmental image data by the image capturing device to generate a second odometer data. In a first fusion stage, the processor fuses the heading angle estimation data and the first odometer data to generate first fusion data. In a second fusion stage, the processor fuses the first fusion data, the heading angle estimation data and the second odometer data to generate pose estimation data corresponding to the localization device.

Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.

Abstract: A chip package structure is provided. The chip package structure includes a chip. The chip package structure includes a conductive ring-like structure over and electrically insulated from the chip. The conductive ring-like structure surrounds a central region of the chip. The chip package structure includes a first solder structure over the conductive ring-like structure. The first solder structure and the conductive ring-like structure are made of different materials.

Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.

Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.

Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A fan guard for a fan container includes a housing and a plurality of wings. The housing has a hollow interior defined by a cylindrical inner surface. The housing extends longitudinally between a first housing end and a second housing end. The plurality of wings is positioned within the hollow interior of the housing. Each wing of the plurality of wings extends radially, from a center of symmetry of the cylindrical inner surface to the cylindrical inner surface. Each wing of the plurality of wings is radially curved between the first housing end and the second housing end.

Abstract: A computer chassis includes walls defining an airspace containing heat-generating components (e.g., storage drives). The airspace is divided into first and second regions, such as by a printed circuit board supporting the heat-generating components within the first region. An air input feeds both the first region and second region. Input air going through the first region first passes by a forward set of heat-generating components before continuing to a rearward set of heat-generating components to extract heat therefrom. Input air going through the second region bypasses the forward set of heat-generating components before being directed out through an air opening partway down the length of the chassis, after which this air passes by a rearward set of heat-generating components to extract heat.

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

Abstract: A multi-function calculator suitable for a neural network architecture is provided. The multi-function calculator includes a plurality of activation function operation circuits and a demultiplexer (DMUX). The plurality of activation function operation circuits are configured to execute a plurality of different activation functions on an input signal respectively. The DMUX is coupled to the plurality of activation function operation circuits. The DMUX is configured to receive an enable signal and a selection signal. The DMUX in an enabled state selects one of the plurality of activation function operation circuits to be enabled according to the selection signal. The enabled activation function operation circuit executes a corresponding activation function on the input signal to generate a corresponding output signal.

Abstract: A display device and driving method thereof are provided. In the display device, a control circuit provides first and second start signals. In a display panel, a pixel array has a plurality of odd and even gate lines. A first and second gate circuits respectively receive the first and second start signals, and respectively provide the sequentially enabled first and second gate signals to odd and even gate lines according to the phases of the first and second start signals, respectively. One of the first and second start signals is phase-shifted by at least one clock cycle from a preset phase during a first scan period that scans from a first side to a second side of the pixel array or during a second scan period that scans from the second side to the first side of the pixel array.

Abstract: A defect detection method for a multilayer daisy chain structure, including: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that the multilayer daisy chain has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

Abstract: A display device and driving method thereof are provided. In the display device, a control circuit provides first and second start signals. In a display panel, a pixel array has a plurality of odd and even gate lines. A first and second gate circuits respectively receive the first and second start signals, and respectively provide the sequentially enabled first and second gate signals to odd and even gate lines according to the phases of the first and second start signals, respectively. One of the first and second start signals is phase-shifted by at least one clock cycle from a preset phase during a first scan period that scans from a first side to a second side of the pixel array or during a second scan period that scans from the second side to the first side of the pixel array.

Abstract: An electronic apparatus with a detection function includes a normal function circuit, a dummy function circuit and a processing module. The normal function circuit operates according to an operation signal. The dummy function circuit operates to generate a result signal according to a test signal and is a small size circuit of the normal function circuit. The test signal and operation signal are same function signals, and the test signal has an electrical characteristic larger than that of the operation signal. The processing module generates the operation signal and the test signal at the same time, accumulates an operation time of the dummy function circuit, and determines whether the dummy function circuit is faulty by detecting the result signal. When the dummy function circuit is faulty, the processing module calculates a remaining lifetime of the normal function circuit according to the test signal, the operation signal and the operation time.

Abstract: The present invention provides a chip-to-chip signal transmission system. Signal transmission is performed between a transmitter of a first chip and a receiver of a second chip through a transmission-metal-pad and a reception-metal-pad. When receiving a driving-testing signal, the transmitter transmits a transmission-testing-coupling signal through the transmission-metal-pad according to the driving-testing signal. A receiving-testing circuit on the first chip receives the transmission-testing-coupling signal through the transmission-testing-metal-pad, and outputs a transmission-testing signal according to the transmission-testing-coupling signal. When receiving the driving-testing signal, a driving-testing circuit on the second chip transmits a receiving-testing-coupling signal through a reception-testing-metal-pad according to the driving-testing signal.

Abstract: A defect detection method for a multilayer daisy chain structure, including: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a daisy chain structure; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that the multilayer daisy chain has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.

Abstract: A defect detection method for a 3D chip and a system using the same are provided. The method includes: generating a plurality of physical models having a defect of at least one defect type based on the at least one defect type of a 3D chip; generating a group of training samples for each of the physical models; generating a classifier model by using a machine learning technique algorithm via scattering parameter values of a training set; measuring an error value by comparing scattering parameter values of a testing set with the classifier model, using the classifier model as a defect model of the defect type based on the error value, and determining that a Through Silicon Via of a single die 3D chip or a stacked die 3D chip has a defect corresponding to the at least one defect type by comparing actual measurements of scattering parameter values.