Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A method for forming an indium gallium nitride quantum well structure is disclosed. The method includes forming a gallium nitride microdisk on a substrate, with the gallium nitride microdisk having an inverted pyramid form and an end face; and forming multiple quantum well layers on the end face, with each quantum well layer including an indium gallium nitride quantum well and a barrier layer. The indium gallium nitride quantum well is grown at a growth temperature adjusted using a trend equation within a temperature range of 480° C. to 810° C.

Abstract: Systems and methods are provided for an electronic device that comprises a core logic circuit coupled to a supply voltage rail and an operating voltage rail. During a standard operation, the supply voltage rail has a supply voltage, the operating voltage rail has an operating voltage, and a post driver voltage rail has an overdrive voltage that is greater than the operating voltage. The electronic device further comprises a first power clamp circuit coupled to the supply voltage rail and the post driver voltage rail, a low-side logic-high voltage rail coupled to the first end of the core logic circuit, and a first power-to-power clamp circuit coupled to the low-side logic-high voltage rail and the post driver voltage rail. The first power-to-power clamp circuit is configured to receive electrostatic discharge (ESD) current between the post driver voltage rail and the low-side logic-high voltage rail.

Abstract: A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.

Abstract: A device includes: a first electrode; a first interfacial layer in contact with the first electrode; a first insertion layer on the first interfacial layer, the first insertion layer having first orthorhombic-phase (O-phase) regions or first monoclinic-phase (M-phase) regions in a first area ratio that exceeds about 70%; a first dielectric layer on the first insertion layer, the first dielectric layer having tetragonal-phase (T-phase) regions in a second area ratio that exceeds those of second O-phase regions and second M-phase regions; a second insertion layer on the first dielectric layer, the second insertion layer having third O-phase regions or third M-phase regions in a third area ratio that exceeds about 70%; a second interfacial layer in contact with the second insertion layer, the second interfacial layer being a different material than the first interfacial layer; and a second electrode on the second interfacial layer.

Abstract: A motor inverter is provided. The motor inverter is coupled to an input power source and a motor and controls the mechanical switch to receive or turn off the input power source. The motor inverter includes primary and secondary auxiliary circuits, a microprocessor, a gate driver, and a motor drive circuit. The primary and secondary auxiliary circuits are coupled to the input power source and outputs first and second output voltages respectively. The microprocessor operates the driving switches of the motor drive circuit through the gate driver to switch the input power source for driving the motor. If the microprocessor determines that the first output voltage is abnormal and the motor rotational speed exceeds a safe speed limit, the microprocessor controls the driving switches to form an active short circuit for stopping the motor, and the microprocessor turns off the mechanical switch for protecting the input power source.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: A motor inverter is provided. The motor inverter is coupled to an input power source and a motor and controls the mechanical switch to receive or turn off the input power source. The motor inverter includes primary and secondary auxiliary circuits, a microprocessor, a gate driver, and a motor drive circuit. The primary and secondary auxiliary circuits are coupled to the input power source and outputs first and second output voltages respectively. The microprocessor operates the driving switches of the motor drive circuit through the gate driver to switch the input power source for driving the motor. If the microprocessor determines that the first output voltage is abnormal and the motor rotational speed exceeds a safe speed limit, the microprocessor controls the driving switches to form an active short circuit for stopping the motor, and the microprocessor turns off the mechanical switch for protecting the input power source.

Abstract: A method for facilitating handwriting practice includes: generating handwriting strokes in response to user input of user-writing strokes; generating an input image that includes the handwriting strokes, and that has a shape similar to a shape of a standard image associated with a standard word character; scaling the input image to generate a scaled image with a size that is the same as a size the standard image; overlapping the standard image and the scaled image; comparing an nth handwriting stroke in the scaled image with an nth standard stroke in a standard order of the standard word character; and when the nth handwriting stroke does not correspond in position to the nth standard stroke, displaying a notification of a stroke order error.

Abstract: A power off indicating apparatus and a power off indicating method thereof are provided. A power off detecting circuit provides a storage voltage to an electrophoretic display when a power is off, so as to control the electrophoretic display to display a power off information. A tag reader resets a display status of the electrophoretic display according to an electronic tag read by the tag reader.

Abstract: A power off indicating apparatus and a power off indicating method thereof are provided. A power off detecting circuit provides a storage voltage to an electrophoretic display when a power is off, so as to control the electrophoretic display to display a power off information. A tag reader resets a display status of the electrophoretic display according to an electronic tag read by the tag reader.

Abstract: A method for facilitating handwriting practice includes: generating handwriting strokes in response to user input of user-writing strokes; generating an input image that includes the handwriting strokes, and that has a shape similar to a shape of a standard image associated with a standard word character; scaling the input image to generate a scaled image with a size that is the same as a size the standard image; overlapping the standard image and the scaled image; comparing an nth handwriting stroke in the scaled image with an nth standard stroke in a standard order of the standard word character; and when the nth handwriting stroke does not correspond in position to the nth standard stroke, displaying a notification of a stroke order error.