Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Abstract: A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. From the plurality of partially-decoded codewords, a codeword having a metric indicating that that codeword is the closest to being successfully decoded by the first error correction decoder and the second error correction decoder is selected. The selected codeword is output to the first error correction decoder.

Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

Abstract: Turbo equalization is performing by using a soft output detector to perform decoding. At least a portion of a local iteration of decoding is performed using a soft output decoder. A metric associated with decoding progress is generated and it is determined whether to perform another local iteration of decoding based at least in part on the metric.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system.

Abstract: Determining a parameter associated with whether a portion of a storage device is defective is disclosed. Determining comprises: obtaining known data associated with the portion; reading back from the portion to produce a read-back waveform; decoding the read-back waveform, including producing statistical information; and determining a parameter associated with whether the portion is defective based at least in part on the statistical information.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.

Abstract: It is decided whether to adjust data associated with a decoder. In the event it is decided to adjust the data associated with the decoder, the data is adjusted to obtain adjusted data and decoding is performed on the adjusted data. In the event it is decided to not adjust the data associated with the decoder, decoding is performed on the data associated with the decoder.

Abstract: A data encoding system includes a data encoder circuit operable to encode each of a number of data sectors with a component matrix of a low density parity check code matrix and to yield an output codeword. The data encoder circuit includes a syndrome calculation circuit operable to calculate and combine syndromes for the data sectors.

Abstract: Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures.

Abstract: A method for detecting a defect in a portion of a storage device is disclosed. Reference data and data read from the portion are compared to determine a number of error bits and a number of error symbols. An error ratio is computed, wherein the error ratio comprises a ratio of the number of error bits to the number of error symbols. A defect is detected based on whether the error ratio exceeds a threshold. In some embodiments, the reference data and the read data are compared to determine an error vector, wherein a bit in the error vector with a value one indicates a bit error in the read data. For each of a plurality of windows of the error vector, a corresponding number of error bits is determined. A defect is detected based on whether any of the numbers of error bits exceeds a threshold.

Abstract: Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures.

Abstract: Second interleaved data is de-interleaved using a second interleaving mapping to obtain encoded data. The second interleaved data includes a copy of constrained data in the same sequence and having the same values as the constrained data. Also, the portion of the second interleaved data that includes the copy of the constrained data satisfies a modulation constraint associated with limiting a number of consecutive events to a maximum number of consecutive events. The encoded data is decoded to obtain first interleaved data and the first interleaved data is de-interleaved using a first interleaving mapping to obtain the constrained data, a copy of which is included in the second interleaved data, where the constrained data satisfies the modulation constraint.

Abstract: A plurality of partially-decoded codewords that have been processed at least once by a first and a second error correction decoder is stored. A plurality of metrics associated with how close a corresponding partially-decoded codeword is to being successfully decoded is stored. From the plurality of partially-decoded codewords, a codeword having a metric indicating that that codeword is the closest to being successfully decoded by the first error correction decoder and the second error correction decoder is selected. The selected codeword is output to the first error correction decoder.

Abstract: A codeword that is associated with one uncorrected codeword in a set of first codewords is selected from a set of third codewords. Error correction decoding is performed on the selected codeword using a third, systematic error correction code.

Abstract: An amount of time and an error rate function are received, where the error rate function defines a relationship between a number of iterations associated with iterative decoding and an error rate. A testing error rate is determined based at least in part on the amount of time. The number of iterations which corresponds to the testing error rate in the error rate function is selected to be a testing number of iterations; the testing error rate and the testing number of iterations are associated with testing storage media using iterative decoding.

Abstract: A data processing system includes a digital data input operable to receive digital data, a digital data values input operable to receive values of the digital data, a loop pulse response estimation circuit operable to calculate a loop pulse response based on the digital data and the values of the digital data and based at least in part on past values of the loop pulse response, and a scaling circuit operable to scale the loop pulse response based at least in part on an absolute sum of the loop pulse response to yield a scaled loop pulse response.

Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.