Patents by Inventor Yu Kun

Yu Kun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190282625
    Abstract: The invention found that first, the feasibility of transfer of tumor resistance and other healthy longevity characters through transplantation of bone marrow mononuclear cells (BMMNC) or hematopoietic stem cells (HSC)/hematopoietic stem and progenitor cells (HSPC) consisting of genetically engineered EKLF gene encoding the hematopoietic transcription factor EKLF. Secondly, the present invention demonstrates expression of EKLF in the long-term hematopoietic stem cells (LT-HSC), and thus EKLF as a target of regulation of hematopoiesis.
    Type: Application
    Filed: September 13, 2017
    Publication date: September 19, 2019
    Applicant: Academia Sinica
    Inventors: Che-Kun James SHEN, Yu-Chiau SHYU, Chun-Hao HUNG
  • Patent number: 10414809
    Abstract: The present invention includes a genetically-modified non-human animal model of longevity and increased health span, which is associated with reduced tumorigenesis and tumor metastasis, as well as related methods for increasing longevity and health span, reducing tumorigenesis and tumor metastasis, and identifying active agents that confer increased longevity or health span, or reduced tumorigenesis or tumor metastasis.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: September 17, 2019
    Assignee: Academia Sinica
    Inventors: Che-Kun James Shen, Yu-Chiau Shyu
  • Patent number: 10416114
    Abstract: A structure of an electrochemical unit includes a substrate, a first metal layer disposed on the substrate, and an array of electrochemical cells disposed on the first metal layer. The array of the electrochemical cells includes a plurality of electrochemical cells. Each of the electrochemical cells includes the first metal layer disposed on the substrate, a first electrode disposed on the first metal layer, a polymer layer disposed on the substrate and adjacent to the first metal layer and the first electrode. A second metal layer is disposed on the polymer layer, and a second electrode is disposed on the second metal layer. A pore is constituted between the polymer layers of every the two electrochemical cells. A cavity located above the first electrode is defined between every the two electrochemical cells, wherein the cavity is communicated with the pore.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: September 17, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jui-Chin Chen, Pei-Jer Tzeng, Tzu-Kun Ku, Yu-Chen Hsin, Yiu-Hsiang Chang
  • Publication number: 20190265568
    Abstract: A display substrate is provided. The display substrate includes a first insulating layer disposed on a substrate, a second insulating layer disposed on the first insulating layer. In particular, the first insulating layer has a first opening and the second insulating layer has a second opening, wherein the first opening and the second opening are partially overlapped. Further, in a cross-sectional view, the first insulating layer corresponding to the first opening has two first bottom ends, and the second insulating layer corresponding to the second opening has two second bottom ends, a location of a first vertical central line between the two first bottom ends is different from a location of a second vertical central line between the two second bottom ends, and the first vertical central line and the second vertical central line are substantially parallel to a normal direction of the surface.
    Type: Application
    Filed: May 2, 2019
    Publication date: August 29, 2019
    Inventors: Hung-Kun CHEN, Yi-Chin LEE, Hong-Kang CHANG, Yu-Chien KAO, Jui-Ching CHU, Li-Wei SUNG, Hui-Min HUANG
  • Publication number: 20190246144
    Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.
    Type: Application
    Filed: November 19, 2018
    Publication date: August 8, 2019
    Inventors: Li-Heng Chen, Chung-Hua Tsai, Tung-Hsing Wu, Lien-Fei Chen, Yu-Kun Lin, Yi-Hsin Huang, Han-Liang Chou
  • Publication number: 20190221260
    Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.
    Type: Application
    Filed: November 6, 2018
    Publication date: July 18, 2019
    Applicant: Winbond Electronics Corp.
    Inventors: Ping-Kun Wang, Shao-Ching Liao, Yu-Ting Chen, Ming-Che Lin, Chien-Min Wu, Chia-Hua Ho
  • Publication number: 20190213109
    Abstract: A computer-implanted method for creating a filtered digital entry includes generating, via a processor implementing a trace generation engine, a trace indicative of successful transactions and erroneous transactions. The processor instantiates a plurality of buffers in a buffer pool each configured to record a trace function boundary. The processor then analyzes each buffer in the buffer pool based on the trace function boundary to evaluate whether each function entry in the trace contains an erroneous transaction. If the processor determines that a function entry contains an erroneous transaction, the processor sets an output flag in a call stack map associated with that function. The processor then generates a filtered digital entry based on the call stack map. The filtered digital entry includes only erroneous transaction data from the trace.
    Type: Application
    Filed: January 9, 2018
    Publication date: July 11, 2019
    Inventors: Al CHAKRA, Zhen Yang SHI, Tian Ming PAN, Yi Xin SONG, Yang ZHANG, Yu Kun WEI, Fu Li BIAN
  • Publication number: 20190213468
    Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Inventors: Frederick CHEN, Ping-Kun WANG, Shao-Ching LIAO, Chih-Cheng FU, Ming-Che LIN, Yu-Ting CHEN, Seow-Fong (Dennis) LIM
  • Patent number: 10319760
    Abstract: An image sensor includes a sensing layer, a number of filter units, and a grid structure. The filter units are disposed on the sensing layer. The grid structure is disposed on the sensing layer and surrounding each of the filter units. The grid structure includes a first partition wall disposed on the sensing layer and located between two adjacent filter units, and a second partition wall disposed on the first partition wall located between the two adjacent filter units. The refractive index of the first partition wall is less than the refractive index of the second partition wall.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: June 11, 2019
    Assignee: Visera Technologies Company Limited
    Inventors: Kuo-Feng Lin, Wu-Cheng Kuo, Chung-Hao Lin, Yu-Kun Hsiao
  • Patent number: 10296234
    Abstract: Embodiments of the present invention relate to a method and apparatus for adjusting throughput of a storage device. The method comprises setting input/output (I/O) delay time of the storage device to be threshold delay time, the threshold delay time being below initial I/O delay time of the storage device. The method further comprises obtaining measured throughput of the storage device, the measured throughput being associated with the threshold delay time. The method further comprises updating the I/O delay time based on a difference between the measured throughput and a target throughput of the storage device to update the measured throughput.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: May 21, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Peng Chen, Kevin Kun Yang, Yu Wen, Venoy Qiang Ma, Harley Hua Wang
  • Patent number: 10292268
    Abstract: A flexible printed circuit board including an annular main board and a plurality of branches connected with the annular main board is provided. Each of the branches includes an extension portion connected with the annular main board and a bonding portion, and an electronic component is adapted to be disposed on the bonding portion. A supporting holder including an annular base, two wing structures, and a plurality of mounting portions is also disclosed, wherein the wing structures extend outward from the annular base and the mounting portions are located on the annular base and the wing structures. Further, a controller including the flexible printed circuit board and the supporting holder aforementioned is disclosed, wherein the annular main board is disposed on the annular base and the branches are disposed on the annular base and the wing structures, such that the bonding portions are located on the mounting portions correspondingly.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 14, 2019
    Assignee: HTC Corporation
    Inventors: Hung-Chi Shui, Ping-Kun Fu, Min-Jung Hsieh, Yu-yu Lin, Jen-Tsung Chang, Chih-Lin Chang
  • Publication number: 20190120293
    Abstract: A porous aerostatic bearing includes a bearing seat and a plurality of porous plunger assemblies. The bearing seat is furnished with a plurality of accommodating holes. By locking the porous plunger assemblies individually into the corresponding accommodating holes, the porous aerostatic bearing with adjustable stiffness can thus be formed, difficulty in maintenance thereof can be lowered, and the entire service expense therefor can be substantially reduced.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 25, 2019
    Inventors: YU-CHIEH KUO, SHAO-YU HSU, CHIA-MENG CHEN, YU-KUN LIN, CHUN-HSIEN SU
  • Publication number: 20190053382
    Abstract: An electronic device package includes a molded case, a plurality of leads and a case lid. The molded case includes integrally formed side walls, end walls, and a bottom wall, which together define an interior for components. Each side wall includes top and bottom portions. The top portion includes first and second surfaces extending downward from a top edge of the side wall. The bottom portion has a top surface that extends away from the interior, a third surface extending downward from the top surface to a bottom edge, and a fourth surface extending downward from the second surface to the bottom wall. The leads are molded in the side wall from the bottom edge to the top edge. Each lead has an end extending above the top edge, and another end extending along the bottom edge of the side wall. The case lid is engaged with the molded case.
    Type: Application
    Filed: October 16, 2018
    Publication date: February 14, 2019
    Inventors: Tung Kong Luk, Yu Kun Liao
  • Patent number: 10054719
    Abstract: A double-lens structure and a method for fabricating the same are provided. The double-lens structure includes a first lens structure formed of a color filter layer having a first refractive index and a second lens structure formed of a micro-lens material layer having a second refractive index and disposed on the first lens structure. The first refractive index of the color filter layer is different from the second refractive index of the micro-lens material layer. An incident light enters the second lens structure and then passes through the first lens structure. Further, a method for fabricating the double-lens structure is also provided.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: August 21, 2018
    Assignee: VisEra Technologies Company Limited
    Inventors: Han-Lin Wu, Yu-Kun Hsiao, Yueh-Ching Cheng
  • Patent number: 10056823
    Abstract: A protection circuit applied to an alternating current (AC) power source includes a sample-and-hold unit, a detection unit, and a discharge signal generation unit. The sample-and-hold unit samples a peak value of a direct current (DC) voltage during each period of a corresponding AC voltage, wherein the AC power source provides the AC voltage. The detection unit generates a detection signal when the DC voltage crosses a reference voltage corresponding to the peak value. The discharge signal generation unit generates a count signal when the discharge signal generation unit does not receive the detection signal within a predetermined time of a period of the AC voltage, accumulates the count signal, and generates a discharge signal to a discharge unit when a number of accumulated count signals is greater than a predetermined value, wherein the discharge unit discharges an X capacitor according to the discharge signal.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: August 21, 2018
    Assignee: Leadtrend Technology Corp.
    Inventors: Ming-Chang Tsou, Meng-Jen Tsai, Yu-Kun Lin
  • Patent number: 10056417
    Abstract: An image-sensor structure is provided. The image-sensor structure includes a substrate with a plurality of photoelectric conversion units formed therein, a plurality of color filters formed above the substrate, wherein the color filters are divided into red color filters, green color filters and blue color filters, a plurality of microlenses correspondingly formed above the color filters, a transparent material layer formed above the microlenses, a first filter blocking infrared (IR) light formed above the transparent material layer, a second filter allowing transmission of visible light formed above the first filter, and a lens module formed above the second filter.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 21, 2018
    Assignee: Visera Technologies Company Limited
    Inventors: Chin-Chuan Hsieh, Yu-Kun Hsiao, Wei-Ko Wang, Li-Kai Lee
  • Patent number: 9978789
    Abstract: An image-sensing device includes a semiconductor substrate, a passive layer, and a light-collecting element. The semiconductor substrate includes a photo-sensing element, and the passive layer is disposed over the semiconductor substrate. The light-collecting element is disposed over the passive layer, and includes first, second and third loops. The first loop has a first width. The second loop surrounds the first loop and has a second width that is less than the first width. The third loop surrounds the first and second loops, and has a third width that is less than the second width. The light-collecting element aligns with the photo-sensing element, and the first, second, and third loops include different refractive indices.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 22, 2018
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Kuo-Feng Lin, Yu-Kun Hsiao, Chin-Chuan Hsieh
  • Publication number: 20180137968
    Abstract: An electronic device includes a molded frame, a core, a coil and a plurality of leads. The molded frame includes central winding bobbin and first and second lateral supports extending laterally outward therefrom. Each of the first and second lateral supports includes a top surface and first and second lower surfaces. The core is disposed about the coil and is supported on the top surfaces of the first and second lateral supports. The leads are formed of conductive material and are molded in the first and second lateral supports. Each of the leads includes a first end portion extending downward from the first lower surface a lateral support, and a second end portion extending along a second lower surface the lateral support. The second lower surface is lower than the first lower surface. The coil is wound about the central winding bobbin. A first end of the coil is affixed to the first end portion of a lead, and a second end of the coil is affixed to the first end portion of another lead.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 17, 2018
    Inventors: Tung Kong Luk, Yu Kun Liao
  • Publication number: 20180122547
    Abstract: An electronic device package includes a molded case and a plurality of leads. The molded case includes integrally formed side walls, end walls, and a top wall, the side walls, end walls and top wall defining an interior for receiving one or more electronic components. Each side wall includes a top portion, an intermediate portion, and a bottom portion. The top portion includes plate-like structure having first and second surfaces extending downward from the top wall. The intermediate portion includes a shelf structure having a shelf surface that extends from the first surface in a direction away from the interior, and a third surface extending downward from the shelf surface. The bottom portion extends downward from the intermediate portion. The leads are molded at least in part of the intermediate portion. Each lead has a first end portion exposed in the interior, and a second end portion extending along a bottom edge of the bottom portion.
    Type: Application
    Filed: October 28, 2016
    Publication date: May 3, 2018
    Inventors: Tung Kong Luk, Yu kun Liao
  • Patent number: 9948839
    Abstract: An image sensor includes a sensing layer, a transparent plate, and a first guided-mode resonance structure. The sensing layer includes sensing units configured to sense a light beam. The transparent plate is located above the sensing layer. The first guided-mode resonance structure is disposed on a first area of the transparent plate, and blocks a first waveband of the light beam from passing through.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 17, 2018
    Assignee: Visera Technologies Company Limited
    Inventors: Wu-Cheng Kuo, Kuo-Feng Lin, Chung-Hao Lin, Yu-Kun Hsiao