Patents by Inventor Yu-Kuo Yang

Yu-Kuo Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119854
    Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 14, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Yu-Kuo Yang, Takao Akaogi, Pauling Chen
  • Publication number: 20210255921
    Abstract: A method of controlling verification operations for error correction of a non-volatile memory device includes the following. A tolerated error bit (TEB) number for error correction of the non-volatile memory device is set to a first value to control verification operations in accordance with the TEB number. After at least one portion of the non-volatile memory device is programmed for a specific number of times, the TEB number is changed from the first value to a second value to control the verification operations in accordance with the TEB number, wherein the second value is greater than the first value and is less than or equal to the TEB threshold. The method may be performed while the at least one portion of the non-volatile memory device is programmed and verified.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: YU-KUO YANG, TAKAO AKAOGI, PAULING CHEN
  • Publication number: 20190148498
    Abstract: An improved passivation structure for GaN field effect transistor comprising at least one dielectric layer formed on a top surface of a GaN field effect transistor and a passivation layer formed on a top surface of the dielectric layer. The GaN field effect transistor has a gate electrode comprising a Schottky contact metal layer, at least one diffusion barrier metal layer and a high conductivity metal layer. The passivation layer is made of a low cure temperature Polybenzoxazole (PBO) which can be cured at a low-temperature. Thereby the intermixing of the Schottky contact metal layer and the the diffusion barrier metal layer are prevented.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventors: Eric LEE, Yu-Kuo YANG, Che-Kai LIN, Forrest CHO, Walter Tony WOHLMUTH
  • Patent number: 7656704
    Abstract: A method for programming a multi-level nitride storage memory cell capable of storing different programming states corresponding to multiple different threshold voltage levels includes providing a variable resistance capable of providing a plurality of different resistance values; connecting a drain side of the nitride storage memory cell to a selected one of the plurality of resistance values that corresponds to one of the multiple threshold voltage levels; and programming the nitride storage memory cell to store one of the program states corresponding to the one of the threshold voltage levels by applying a programming voltage to the drain side through the selected resistance.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: February 2, 2010
    Assignee: Winbond Electronics Corp.
    Inventors: Po-An Chen, Yu-Kuo Yang, Tzu-Ching Chuang, Hsiu-Han Liao
  • Publication number: 20080019181
    Abstract: A method for programming a multi-level nitride storage memory cell capable of storing different programming states corresponding to multiple different threshold voltage levels includes providing a variable resistance capable of providing a plurality of different resistance values; connecting a drain side of the nitride storage memory cell to a selected one of the plurality of resistance values that corresponds to one of the multiple threshold voltage levels; and programming the nitride storage memory cell to store one of the program states corresponding to the one of the threshold voltage levels by applying a programming voltage to the drain side through the selected resistance.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Inventors: Po-An Chen, Yu-Kuo Yang, Tzu-Ching Chuang, Hsiu-Han Liao