Patents by Inventor Yu-Lam Ho

Yu-Lam Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6432759
    Abstract: Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped source region, a lightly doped source region, a gate or channel region, a lightly doped drain region, and a moderately doped drain region, arranged consecutively in that order, with the channel region adjacent to the gate having opposite electrical conductivity type to the electrical conductivity type of the source and drain regions. The source region and drain region are formed by ion implantation with ion kinetic energies of 40 keV or more, to increase the width and depth of charge carrier flow in these regions and to thereby reduce the substrate current associated with the device to less than one &mgr;Amp/&mgr;m.
    Type: Grant
    Filed: June 14, 1994
    Date of Patent: August 13, 2002
    Assignee: LSI Logic Corporation
    Inventor: Yu-Lam Ho
  • Patent number: 6093936
    Abstract: A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: July 25, 2000
    Assignee: LSI Logic Corporation
    Inventors: Abraham Yee, Sheldon Aronowitz, Yu-Lam Ho
  • Patent number: 5717238
    Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: February 10, 1998
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi Padmanabhan, Douglas T. Grider, Chi-Yi Kao
  • Patent number: 5585286
    Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: December 17, 1996
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Gobi Padmanabhan, Douglas T. Grider, Chi-Yi Kao
  • Patent number: 5468974
    Abstract: Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: November 21, 1995
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Yen-Hui J. Ku, Yu-Lam Ho