Patents by Inventor Yu Li

Yu Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250250249
    Abstract: The present invention provides novel substituted benzimidazole derivatives used as DAAO inhibitors and for treatment and/or prevention of neurological disorders.
    Type: Application
    Filed: April 25, 2025
    Publication date: August 7, 2025
    Inventors: Yufeng Jane TSENG, Yu-Li LIU, Chung-Ming SUN, Wen-Sung LAI, Chih-Min LIU, Hai-Gwo HWU
  • Publication number: 20250243040
    Abstract: A hoist for hoisting servers of an immersion cooling tank comprises a guide, a moving base, a hoisting arm, a hanging component, a drive component. The guide is located on the immersion cooling tank and extended horizontally. The moving base is located on the guide and movable along the guide. The hoisting arm is located on the moving base and is rotatable relative to the moving base around a vertical axis. The hanging component is used for hanging the server. The drive component is located on the hoisting arm and is connected to the hanging component. The drive component is used for lifting and dropping the hanging component and the server hanged on the hanging component. A hoisting system is also disclosed.
    Type: Application
    Filed: May 27, 2024
    Publication date: July 31, 2025
    Inventors: MING-HUA DUAN, Fang-Xing Yang, Han-Yu Li
  • Publication number: 20250238651
    Abstract: The invention relates to an emotion recognition system based on a hyperdimensional computing (HDC) accelerator, which performs emotion recognition by analyzing electroencephalogram (EEG) spectrograms and utilizing machine learning. The emotion recognition system introduces hyperdimensional computing accelerator for affective computing based on 16-channel EEG spectrograms. The system features two continuous item memories and spatial-temporal encoders to improve recognition accuracy. In feature extraction, short-time Fourier Transform (STFT), baseline normalization, and quantization are employed. The advantages of the algorithm include hardware-friendly and highly parallel efficient computation, rapid convergence with single-pass training, and the capability for few-shot learning. Additionally, a dedicated accelerator for HDC is designed, enabling high-speed and energy-efficient results while maintaining comparable accuracy.
    Type: Application
    Filed: October 2, 2024
    Publication date: July 24, 2025
    Inventors: Wai-Chi Fang, Jia-Yu Li
  • Publication number: 20250236070
    Abstract: This invention discloses a self-centering and self-mixing semi-flexible coaxial nozzle capabilities, and its manufacturing method. The invention comprises an upper cover, a semi-flexible inner needle, a three-way casing, a three-way convex platform and an outer needle, wherein the bottom of the upper cover is screwed on the three-way casing; the central part of the three-way casing is provided with the semi-flexible inner needle and the outer needle is screwed on the bottom of the three-way casing; the semi-flexible inner needle extends to the inside of the outer needle through the head of the three-way casing; and two three-way convex platform are screwed on the left and right side surfaces of the three-way casing. The invention has the following beneficial effects: the semi-flexible inner needle self-centers via fluid dynamics to correct coaxiality errors; the three-way mixer enables passive material blending; and a sealed assembly (fixed plate, fixture block) ensures leak-proof rigidity.
    Type: Application
    Filed: April 9, 2025
    Publication date: July 24, 2025
    Inventors: Yu Li, Pingyan Bian, Jianhui Liu, Xiaohui Zhang, Haijun Qu, Jianping Wang, Shilei Li, Hua Li, Yahui Qiao, Shengzhao Qiao
  • Publication number: 20250234592
    Abstract: Various embodiments of the present disclosure provide a method for forming a semiconductor device structure. The method includes forming a fin structure from a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked, removing edge portion of the second semiconductor layers by an etch process, after the etch process, subjecting the second semiconductor layers to a post-treatment process to remove residues from exposed surfaces of the second semiconductor layers. The method also includes after the post-treatment process, subjecting the treated surfaces of the second semiconductor layers to a pre-clean process. The method further includes forming an inner spacer in contact with the treated surfaces of the second semiconductor layers.
    Type: Application
    Filed: January 15, 2024
    Publication date: July 17, 2025
    Inventors: Bo Wei LAN, Chih-Teng LIAO, Yu-Li LIN, Ya-Wei LIAO
  • Publication number: 20250231779
    Abstract: An interface generation method includes splitting a render tree into a plurality of render sub-trees, concurrently converting the plurality of render sub-trees into a rendering instruction through a plurality of threads, and further generating an interface based on the rendering instructions.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 17, 2025
    Inventors: Jian Chen, Yu Li, Tanqi Yu, Xingchun Ji, Yaoying Zhou, Xinpeng Wang
  • Patent number: 12361914
    Abstract: A vertical synchronization signal-based control method. The method includes the electronic device draws a first layer of a first application in response to a first vertical synchronization signal, and buffers the first layer to a first buffer queue. The electronic device performs, in response to a second vertical synchronization signal, layer composition on the layer buffered in the first buffer queue, to obtain an image frame. The electronic device adjusts a signal period of the first vertical synchronization signal to first duration if a quantity of layers buffered in the first buffer queue is less than a first preset threshold, where the first duration is less than a signal period of the second vertical synchronization signal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 15, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jian Chen, Yu Li, Tanqi Yu, Wei Tan, Yuehai Zhou, Liang Wang
  • Patent number: 12361711
    Abstract: A slow-motion video shooting method includes detecting that a preset motion occurs on a main object in a video stream; determining a first video clip in the video stream based on the preset motion; determining a first frame rate based on the preset motion; and processing the first video clip based on the first frame rate to obtain a second video clip, where a play time of the second video clip at a target play frame rate is greater than a collection time of the first video clip, and the first frame rate is greater than the target play frame rate. When a main object for shooting moves, the first video clip, for example, a highlight clip, is obtained from the video stream, so that an electronic device can accurately capture a highlight moment of the main object.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: July 15, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Rui Chen, Yu Li, Di Zhang, Bin Chen, Xingguang Song
  • Patent number: 12343625
    Abstract: A refresh rate switching method and an electronic device are provided. In the method, the electronic device dynamically switches a corresponding screen refresh rate by determining whether a current display image is a high frame rate scenario or a standard frame rate scenario. In the high frame rate scenario, a relatively high screen refresh rate is used to support a high display frame rate. In this way, a user can obtain experience of the high display frame rate, and the display image is smooth without motion blur. In the standard frame rate scenario, a default low screen refresh rate is used to reduce power consumption of an entire system.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: July 1, 2025
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jun Xu, Yu Li, Liang Wang, Rui Ning, Qiangguo Jiang
  • Publication number: 20250210857
    Abstract: The disclosure provides an integrated multi-feed antenna, including a first conductor layer, a second conductor layer, and multiple feeding conductor lines. The second conductor layer has a first center position. The second conductor layer has a closed slit structure. The closed slit structure surrounds the first center position to encircle forming a center region. The second conductor layer is spaced apart from the first conductor layer at a first interval. Each of the feeding conductor lines has one end electrically connected or electrically coupled to the second conductor layer, and each has another end electrically connected to a signal source. Each of the feeding conductor lines excites the second conductor layer to generate at least one resonant mode. The resonant modes cover at least one identical wireless communication band.
    Type: Application
    Filed: December 26, 2023
    Publication date: June 26, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Yu Li, Wei Chung, Kin-Lu Wong
  • Publication number: 20250209425
    Abstract: A computer-implemented method for automating actions across applications includes providing a user interface of an object within a first application to a user computing system. The method further includes receiving an input from the user computing system via the user interface, where the input is associated with requesting an action to be taken with a second application, and where the action uses content associated with the object of the first application. Additionally, the method includes performing the action with the second application based at least in part on the input being received.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Inventors: Behnoosh Hariri, Yu Li, Gregory George Galante, Christopher Gregory Tong, Dennis Yung-Chi Hu
  • Publication number: 20250211419
    Abstract: Provided are an inference method and apparatus for a large language model, a device, and a storage medium. The inference method for the large language model includes: performing encryption on a target input text to obtain a target input ciphertext; sending the target input ciphertext to a server so that an encrypted model is used for performing inference on the target input ciphertext by the server to obtain a target result ciphertext; receiving the target result ciphertext sent by the server; and performing decryption on the target result ciphertext to obtain a target result plaintext.
    Type: Application
    Filed: June 20, 2024
    Publication date: June 26, 2025
    Inventors: Zhiyu CHEN, Jiwen ZHOU, Jingbo ZHOU, Zeyu CHEN, Chenfu BAO, Xia WANG, Sheng GUO, Huan WANG, Yu LI, Liguo XU, Suochao ZHANG
  • Publication number: 20250210869
    Abstract: A heterogeneous material integration antenna includes grounded conductive layer, dielectric layer, dielectric pieces, and antenna conductive structure. Dielectric layer is spaced apart from grounded conductive layer by first distance, and dielectric layer has first dielectric constant. Dielectric pieces each are formed in dielectric layer. Dielectric pieces are adjacent to one another and arranged in dielectric array. Outline of outermost edge of dielectric array forms dielectric region having area. The adjacent ones of dielectric pieces are spaced apart from each other by second distance. Dielectric pieces each have second dielectric constant. Magnitude of second dielectric constant is higher than magnitude of first dielectric constant. Antenna conductive structure is disposed between grounded conductive layer and dielectric array. Antenna conductive structure is electrically connected to signal source.
    Type: Application
    Filed: June 4, 2024
    Publication date: June 26, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-An LU, Wei-Yu LI, Wei CHUNG, Jiun-Jang YU
  • Publication number: 20250199556
    Abstract: A circuit includes an operational amplifier configured to output a driving signal according to a feedback voltage associated with an output voltage and a reference voltage, a pass gate circuit comprising switches in current paths, and hysteresis comparators connected to the operational amplifier and configured to generate control signals to separately turn on or off the switches in the current paths in response to the driving signal.
    Type: Application
    Filed: February 26, 2025
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng CHEN, Yen-Lin LIU, Chia-Wei HSU, Jo-Yu WU, CHANG-FEN HU, Shao-Yu LI, Bo-Ting CHEN
  • Publication number: 20250189827
    Abstract: Systems and methods for enabling higher uniform performance and higher voltage operation for micro-OLED displays, manufacturing a meniscus lens including thermo-forming a functional optical layer and printing a lens element over the formed functional optical layer, using a hybrid process used to form a functionalized lens having a controlled surface profile, modeling the polarization properties of a human eye using a polymer thin film, and improving optical sparce eye-tracking by collecting an optical output signal from each detector through a corresponding optical fiber, and determining a gaze direction of a user's eye based on the electrical signal may be disclosed.
    Type: Application
    Filed: December 4, 2024
    Publication date: June 12, 2025
    Inventors: Gang Chen, Ahmet Tura, Suhui Lee, Gyungmin Kim, Tao-Hua Lee, Cheonhong Kim, Yung-Yu Hsu, Min Hyuk Choi, Amir Amirkhany, Yu Li, Rongzhi Huang, Sawyer Miller, Zhenye Li, Junren Wang, Redeen Alexandre E Mendoza Duran, Khalid Omer, Weihan Zhang, Mantas Zurauskas, Scott Charles McEldowney, Lu Lu, Brian Schowengerdt, Jun Yan, Michal Makowski
  • Publication number: 20250194200
    Abstract: A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.
    Type: Application
    Filed: January 28, 2025
    Publication date: June 12, 2025
    Inventors: Yan-Ting SHEN, Yu-Li LIN, Jui Fu HSIEH, Chih-Teng LIAO
  • Publication number: 20250175492
    Abstract: An anomaly detection-based attention purification graph defense method is provided, which includes: Step 1: selecting an anomaly detection algorithm, passing an input graph into an anomaly detection module, and obtaining potential abnormal edges, wherein the obtained result is specifically a two-dimensional matrix named linkpred; Step 2: passing the linkpred matrix obtained in Step 1 and other required training parameters into an ADGAT model for training, and purifying an attention layer in the training process by linkpred; Step 3: using the trained model to generate graph node features to complete a specific downstream graph task. In the downstream graph task with high security requirements, the method can enhance the robustness of the model on the premise of defending the inherent noise and malicious disturbance in graph data and ensuring the performance of GNNs.
    Type: Application
    Filed: November 11, 2024
    Publication date: May 29, 2025
    Inventors: Youhuizi LI, Yuyu YIN, Yi WANG, Tingting LIANG, Yu LI
  • Patent number: 12315864
    Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chi Yu, Jui Fu Hsieh, Yu-Li Lin, Chih-Teng Liao, Yi-Jen Chen
  • Patent number: 12315777
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Elizabeth Nofen, Shripad Gokhale, Nick Ross, Amram Eitan, Nisha Ananthakrishnan, Robert M. Nickerson, Purushotham Kaushik Muthur Srinath, Yang Guo, John C. Decker, Hsin-Yu Li
  • Patent number: 12312326
    Abstract: The present invention provides novel substituted benzimidazole derivatives used as DAAO inhibitors and for treatment and/or prevention of neurological disorders.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 27, 2025
    Assignees: National Taiwan University, National Yang Ming Chiao Tung University, National Health Research Institutes
    Inventors: Yufeng Jane Tseng, Yu-Li Liu, Chung-Ming Sun, Wen-Sung Lai, Chih-Min Liu, Hai-Gwo Hwu