Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display, such as an organic light-emitting diode (OLED) display, are provided. In one example, a sub-pixel includes a substrate, adjacent overhang structures, an anode, an OLED material, a cathode, an encapsulation layer stack. The encapsulation layer stack includes a first layer, a second layer disposed over the first layer, and a third layer. The first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each overhang structure, and a third portion disposed under an underside surface of an extension of each overhang structure. A gap is defined by contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed over the second layer outside of the gap.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a capacitor over a substrate. The capacitor includes a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers and dielectric layers define a base structure and a first protrusion structure extending downward from the base structure towards a bottom surface of the substrate. The first protrusion structure comprises one or more surfaces defining a first cavity. A top of the first cavity is disposed below the base structure.

Abstract: A method of manufacturing a semiconductor memory device, including steps of providing a substrate, forming word lines extending in a first direction in the substrate, forming bit lines extending in a second direction over the word lines, forming partition structures between the bit lines and right above the word lines, forming storage node contacts in spaces defined by the bit lines and the partition structures, wherein a portion of each of the storage node contacts protruding from top surfaces of the bit lines and the partition structures is contact pad, forming a first dielectric layer on the contact pads, the bit lines and the partition structures, forming a second dielectric layer on the first dielectric layer, and performing an etch back process to remove parts of the second dielectric layer, so that only parts of the second dielectric layer on sidewalls of the contact pads remain.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer.

Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

Abstract: A method for uplink transmission performed by a UE is provided. The method includes: receiving a first configured grant configuration that allocates a first PUSCH duration; receiving a second configured grant configuration that allocates a second PUSCH duration, wherein the second PUSCH duration overlaps with the first PUSCH duration; obtaining a first HARQ process ID for the first PUSCH duration, then determining whether a first configured grant timer associated with the first HARQ process ID is running; obtaining a second HARQ process ID for the second PUSCH duration, then determining whether a second configured grant timer associated with the second HARQ process ID is running; and selecting one of the first PUSCH duration and the second PUSCH duration for an uplink transmission based on whether the first configured grant timer is running and whether the second configured grant timer is running.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A base station for wireless communication is provided. The base station transmits to a user equipment (UE) a first Radio Resource Control (RRC) configuration and the second RRC configuration. The first RRC configuration is for configuring a first semi-persistent scheduling (SPS) physical downlink shared channel (PDSCH) and includes a first parameter indicating its relative priority for when the first SPS PDSCH overlaps with another SPS PDSCH in a time domain The second RRC configuration, which overlaps the first SPS PDSCH, is for configuring a second SPS PDSCH and includes a second parameter indicating its relative priority for when the second SPS PDSCH overlaps with another SPS PDSCH in the time domain.

Abstract: Mass transfer equipment including a base stage, a first substrate stage, a second substrate stage, at least one laser head and a servo motor module is provided. The first substrate stage is adapted to drive a target substrate to move along a first direction. The second substrate stage is adapted to drive at least one micro device substrate to move along a second direction. The at least one laser head is adapted to move to a target position of the second substrate stage and emits a laser beam toward the at least one micro device substrate. At least one micro device is separated from a substrate of the at least one micro device substrate and connected with the target substrate after the irradiation of the laser beam. The servo motor module is used for driving the first substrate stage, the second substrate stage and the at least one laser head to move.

Abstract: A radio frequency (RF) match assembly for a chemical vapor deposition processing chamber. The assembly includes a top electrically insulating column and a bottom electrically insulating column. The assembly further includes a one-piece RF match strap that has a head, a main body and a body extension. The main body of the one-piece RF match strap is configured to extend through the top electrically insulating column and the bottom electrically insulating column. A flexible chamber lid strap connects the processing chamber to the top of the one-piece RF match strap.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

Abstract: A device includes source/drain regions, a gate structure, a source/drain contact, and a tungsten structure. The source/drain regions are over a substrate. The gate structure is between the source/drain regions. The source/drain contact is over one of the source/drain regions. The tungsten structure is over the source/drain contact. The tungsten structure includes a lower portion and an upper portion above the lower portion. The upper portion has opposite sidewalls respectively set back from opposite sidewalls of the lower portion of the tungsten structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

Abstract: Embodiments are directed to a method of operating a plasma processing system by retrofitting one or more components thereof. The method includes removing a holder from a gas supply mechanism of the plasma processing system. The holder includes a gas injector that is configured to provide gas received from a gas source to a plasma chamber of the plasma processing system. The method further includes reducing a size of a guide pin of the holder, installing the holder including the guide pin having the reduced size in the gas supply mechanism, and rotating the gas injector to change a flow of gas through the gas injector.