Patents by Inventor Yu Liao

Yu Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253893
    Abstract: A system and a method for automatically adjusting a beam direction of a reflector are provided. The system includes: a reflector for reflecting, refracting, or transmitting incident waves of network signals to a specified area; a database, storing optimized setting combinations for specified areas that include an altitude of the reflector and angles thereof with respect to the specified area, making signals of the specified area have maximum intensity; a communication module, receiving a trigger signal; a computing and processing module, retrieving from the optimized setting combination for the specified area according to the area name of the trigger signal; and a control module, adjusting the altitude and angles of the reflector according to the optimized setting combination. The disclosure can automatically detect a specified area needing network service and automatically adjust the reflector for signal intensity enhancement.
    Type: Application
    Filed: April 25, 2024
    Publication date: August 7, 2025
    Inventors: CHUN-CHIEH KUO, HUA-PEI CHIANG, CHYI-DAR JANG, CHI-HUNG LIN, TSUNG-JEN WANG, CHE-YU LIAO, CHI-EN CHIEN, HAO CHEN
  • Publication number: 20250254885
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. The semiconductor device structure includes a device layer having a first side and a second side opposing the first side, and a first interconnect structure disposed over the first side of the device layer. The first interconnect structure includes a first interconnect-level layer, a second interconnect-level layer disposed over the first interconnect-level layer, wherein the second interconnect-level layer comprises an array of vertical-type memory cell devices. The semiconductor device structure also includes a third interconnect-level layer disposed over the second interconnect-level layer.
    Type: Application
    Filed: February 7, 2024
    Publication date: August 7, 2025
    Inventors: Shih-Yu LIAO, Chung-Liang CHENG
  • Publication number: 20250244544
    Abstract: A semiconductor photonic package includes a first photonic die and a second photonic die laterally disposed over a substrate, a light divergence structure disposed over the first photonic die and beside the second photonic die, and a light source disposed over the light divergence structure. The light source provides an optical signal vertically to the first photonic die, and the optical signal is reflected or refracted to be laterally directed to the second photonic die by the light divergence structure. The light divergence structure allows the optical signals to be directed to optical signal receivers in various locations and/or at various depths, and thus improves signal receiving in a multi-type semiconductor photonic package.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 31, 2025
    Inventors: HSIANG-TING CHENG, SHIH-YU LIAO, TAO-CHENG LIU
  • Publication number: 20250248031
    Abstract: A semiconductor fabrication method includes providing a substrate with a logic device formed on the substrate and a plurality of metal routing layers disposed above the logic device and substrate with metal routing connected to the logic device, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias, and a planarized oxide layer; forming a fin structure over the oxide layer in the upper metal routing layer from IGZO; forming a high-K dielectric layer over the oxide layer and the fin structure; forming a storage gate over channel regions of the fin structure; forming a control gate on a first side and a second side of the storage gate; and connecting at least one of the control gate and a source/drain regions of the fin structure to the logic device using VIAs and metal lines.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yu Liao, Chung-Liang Cheng
  • Publication number: 20250248030
    Abstract: A semiconductor fabrication method includes providing a substrate with a logic device formed on the substrate and a plurality of metal routing layers disposed above the logic device and substrate with metal routing connected to the logic device, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias, and a planarized oxide layer; forming a fin structure over the oxide layer in the upper metal routing layer from IGZO; forming a high-K dielectric layer over the oxide layer and the fin structure; forming a storage gate over channel regions of the fin structure; forming a first control gate on a first side of the storage gate; forming a second control gate on a second side of the storage gate; and connecting the first control gate to a first word line and the second control gate to a second word line.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Yu Liao, Chung-Liang Cheng
  • Patent number: 12373563
    Abstract: A computer system for failing a secure boot in a case tampering event comprises a microcontroller unit (MCU); a trusted platform module (TPM), for generating random bytes for a secure boot of the computer system; a bootloader, for storing information comprising the random bytes in the MCU and at least one hardware of the computer system and performing the secure boot, wherein the TPM is comprised in the bootloader; an operating system (OS), for performing the secure boot; and at least one sensor, coupled to the MCU, for detecting a case tampering event, and transmitting a signal for triggering a deletion of the random bytes, if the case tampering event happens. The MCU performs the operation of deleting the random bytes stored in the MCU and the at least one hardware according to a power supply, in response to the signal.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: July 29, 2025
    Assignee: Moxa Inc.
    Inventors: Chia-Te Chou, Tsung-Yi Lin, Yoong Tak Tan, Hsin-Ju Wu, Jian-Yu Liao, Che-Yu Huang, Tsung-Li Fang, Kuo-Chen Wu, Chih-Yu Chen
  • Patent number: 12369076
    Abstract: Methods, apparatus circuitry, and storage media are described for mobile-terminated packet transmissions. In one embodiment, an apparatus of a control plane device configured to operate within an evolved packet network core identifies a first service flow event trigger associated with a first packet data unit (PDU) session and processes a path reselection for a first PDU session in response to the first service flow event trigger, wherein the path reselection determines a new gateway for the first PDU session resulting from the path reselection. Transmission of a change notification to an application server controller associated with the first PDU session is initiated in response to the path reselection. Transmission of a routing update to the new gateway in response to the path reselection is also initiated. In various embodiments, the trigger may be a mobility event, a load balancing event, or operations in association with an application server controller.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: July 22, 2025
    Assignee: Apple Inc.
    Inventors: Ching-Yu Liao, Mohammad Mamunur Rashid, S. M. lftekharul Alam, Rath Vannithamby
  • Publication number: 20250230039
    Abstract: To fabricate a microelectromechanical (MEMS) arm, a release structure is disposed on a base structure having an anchor structure. A lower protective dielectric layer is deposited on the release structure. An arm structure is formed on the lower protective dielectric layer and on the anchor structure. The release structure is removed by etching with a fluorine-based etchant to form the MEMS arm secured to the anchor structure and including the arm structure and the lower protective dielectric layer. The anchor structure may be a first electrode, and the base structure further includes a second electrode and a spacer interposed between the first electrode and the second electrode. The release structure disposed on the second electrode and on the spacer, and the etching further removes the spacer. The result is a capacitive MEMS structure with the cantilevered arm capacitively coupled with the second electrode.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 17, 2025
    Inventor: Shih-Yu Liao
  • Publication number: 20250215471
    Abstract: A genetically engineered microorganism is provided. The genetically engineered microorganism has a higher expression level of acid-tolerant gene than a source microorganism. The acid-tolerant gene includes at least one of dsdA, dcuC and glaA. A method of preparing the genetically engineered microorganism and a method of producing a target chemical using the genetically engineered microorganism are also provided.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Ching CHANG, Hung-Yu LIAO, Jhong-De LIN, Jie-Len HUANG, Ke-Ming LIANG
  • Publication number: 20250215470
    Abstract: A genetically modified microorganism producing black dyes is provided. The genetically modified microorganism producing black dyes includes a first exogenous nucleic acid and a second exogenous nucleic acid. The first exogenous nucleic acid includes a nucleic acid encoding an ATP-binding cassette transporter (ABC transporter), wherein the nucleic acid encoding an ATP-binding cassette transporter includes a nucleic acid for ped gene cluster. The second exogenous nucleic acid includes a nucleic acid encoding tyrosinase.
    Type: Application
    Filed: December 10, 2024
    Publication date: July 3, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Ching CHANG, Jhong-De LIN, Hung-Yu LIAO, Ya-Lin LIN, Hsiang-Yuan CHU
  • Publication number: 20250221091
    Abstract: Some implementations described herein provide techniques and apparatuses provide a semiconductor device including a photonics device having a backside transmissive region and methods of manufacturing. The semiconductor device includes a first semiconductor device stacked over a second semiconductor device, where the first semiconductor device includes a photodiode structure and the second semiconductor device includes the backside transmissive region. The backside transmissive region, which is below the photodiode structure of the first semiconductor device, includes a trench structure having highly reflective structures and/or properties to maintain an optical power of light waves propagating through the backside transmissive region. An absence of structures within the trench structure lessens a likelihood of interferences which may cause a transmission loss (e.g.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Shih-Yu LIAO, Tao-Cheng LIU
  • Publication number: 20250215221
    Abstract: A low dielectric high Tg resin composition includes a resin system, a halogen-free flame retardant, a coupling agent, and an inorganic filler. The resin system includes a low dielectric resin, a crosslinking agent, and a polyindene resin which are each added in a specific weight percentage. The low dielectric resin is formed from a monomer composition including styrene, divinylbenzene, and ethylene. Therefore, the low dielectric high Tg resin composition has a glass transition temperature not less than 200° C., and the low dielectric high Tg resin composition after being cured has a dielectric constant (Dk) between 3.0 and 3.2 and a dielectric loss factor (Df) less than 0.0013 at 10 GHz. Based on the above, a prepreg and a metal clad laminate applying the low dielectric high Tg resin composition are further provided.
    Type: Application
    Filed: March 22, 2024
    Publication date: July 3, 2025
    Inventors: TE-CHAO LIAO, WEI-RU HUANG, HUNG-YI CHANG, CHIA-LIN LIU, Ren-Yu Liao
  • Publication number: 20250215173
    Abstract: A resin composition and a method for manufacturing the same, and a prepreg are provided. The method includes: implementing a ball mill process upon a filler to form a rough layer onto a surface of the filler, and then forming a chemically modified layer by attaching a polysiloxane onto the rough layer, so as to obtain a modified filler; and adding the modified filler into a heat resistant resin to form the resin composition. The polysiloxane has a functional group. An equivalent weight of the polysiloxane ranges from 1,500 g/mol to 10,000 g/mol.
    Type: Application
    Filed: April 4, 2024
    Publication date: July 3, 2025
    Inventors: TE-CHAO LIAO, Ren-Yu Liao, HUNG-YI CHANG, CHIA-LIN LIU
  • Publication number: 20250220888
    Abstract: One aspect of the present disclosure pertains to a memory device. The memory device includes a semiconductor feature made of a compound semiconductor material. The semiconductor features includes a first portion as a first source/drain (S/D) feature, a second portion as a channel, and a third portion as a second S/D feature. The first portion is above the second portion and the second portion is above the third portion, and the second portion vertically extends from the first portion to the third portion. The memory device includes a gate structure horizontally wrapping around the second portion and a capacitor structure in direct contact with and wrapping around the semiconductor feature.
    Type: Application
    Filed: January 2, 2024
    Publication date: July 3, 2025
    Inventors: Shih-Yu Liao, Chung-Liang Cheng
  • Publication number: 20250215205
    Abstract: A low dielectric resin composition for improvement of processability includes a resin system, a halogen-free flame retardant, hollow spherical silica, and a coupling agent. The resin system includes a polyphenylene ether resin, a crosslinking agent, and a vinyl-containing elastomer which are each added in a specific weight percentage. The hollow spherical silica has a specific gravity between 0.4 g/cm3 and 0.6 g/cm3 and an average particle size (D50) between 2.0 ?m and 3.0 ?m. Therefore, the low dielectric resin composition after being cured has a dielectric constant (Dk) between 2.75 and 3.05 and a dielectric loss factor (Df) of less than 0.002 at 10 GHz. Based on the above, a prepreg and a metal clad laminate applying the low dielectric resin composition are further provided.
    Type: Application
    Filed: March 25, 2024
    Publication date: July 3, 2025
    Inventors: TE-CHAO LIAO, WEI-RU HUANG, HUNG-YI CHANG, CHIA-LIN LIU, Ren-Yu Liao
  • Patent number: 12315981
    Abstract: A transmission line device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.
    Type: Grant
    Filed: November 25, 2022
    Date of Patent: May 27, 2025
    Assignees: UNIMICRON TECHNOLOGY CORP., NATIONAL TAIWAN UNIVERISTY
    Inventors: Yu-Kuang Wang, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
  • Publication number: 20250132695
    Abstract: A method comprises: providing a substrate comprising a first trench; forming an etch stop layer on the substrate; forming a silicon sacrificial region in the first trench; forming a first micromechanical arm array in the silicon sacrificial region; forming a second micromechanical arm array in the silicon sacrificial region; patterning and etching a top portion of each micromechanical arm in the first micromechanical arm array to form a protrusion; forming at least one polysilicon sacrificial layer on the micromechanical arms in the second micromechanical arm array and the micromechanical arms in the second micromechanical arm array, wherein the protrusion of each micromechanical arm in the first micromechanical arm array remains exposed; forming a metal layer; and removing the silicon sacrificial region and the at least one polysilicon sacrificial layer to create a cavity.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 24, 2025
    Inventors: Shih-Yu Liao, Tsai-Hao Hung
  • Patent number: 12283637
    Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: April 22, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
  • Publication number: 20250118594
    Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei SU, Hsin-Ping CHEN, Yung-Hsu WU, Li-Ling SU, Chan-Yu LIAO, Shao-Kuan LEE, Ting-Ya LO, Hsin-Yen HUANG, Hsiao-Kang CHANG
  • Publication number: 20250115756
    Abstract: The disclosure provides a resin composition, a substrate, and a copper clad laminate, wherein the resin composition includes a naphthalene ring epoxy resin, a bismaleimide resin, a crosslinking agent, polysiloxane, an accelerator, and a filler.
    Type: Application
    Filed: October 31, 2023
    Publication date: April 10, 2025
    Applicant: NAN YA PLASTICS CORPORATION
    Inventors: Te-Chao Liao, Hung-Yi Chang, Chia-Lin Liu, Ren-Yu Liao