Abstract: A method comprises: providing a substrate comprising a first trench; forming an etch stop layer on the substrate; forming a silicon sacrificial region in the first trench; forming a first micromechanical arm array in the silicon sacrificial region; forming a second micromechanical arm array in the silicon sacrificial region; patterning and etching a top portion of each micromechanical arm in the first micromechanical arm array to form a protrusion; forming at least one polysilicon sacrificial layer on the micromechanical arms in the second micromechanical arm array and the micromechanical arms in the second micromechanical arm array, wherein the protrusion of each micromechanical arm in the first micromechanical arm array remains exposed; forming a metal layer; and removing the silicon sacrificial region and the at least one polysilicon sacrificial layer to create a cavity.

Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.

Abstract: The disclosure provides a resin composition, a substrate, and a copper clad laminate, wherein the resin composition includes a naphthalene ring epoxy resin, a bismaleimide resin, a crosslinking agent, polysiloxane, an accelerator, and a filler.

Abstract: The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

Abstract: An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.

Abstract: An optical image capturing system, along an optical axis from an object side to an image side, includes a lens and an optical filter. The lens has refractive power. The optical filter is adjacent to the lens. The lens and/or the optical filter include or includes at least one visible light absorbing ingredient, absorb or absorbs a visible light with a wavelength range from 400 nm to 700 nm, and allows a light with a wavelength range greater than 800 nm to pass correspondingly. In another embodiment, a plurality of lenses is provided. At least one of the lenses is a filter lens. The filter lens includes the at least one visible light absorbing ingredient, so that the optical image capturing system could absorb the visible light and has a high transmittance of the infrared, thereby improving a light receiving efficiency and a working quality.

Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a topside oxide layer and a silicon layer that is formed on the topside oxide layer. The structure further includes a rib waveguide component formed in the silicon layer and that includes contact holes. The contact holes include a contact hole depth, and a contact hole trench that is formed in the silicon layer and which has a first sidewall, a second sidewall, and a bottom surface. The contact hole further includes a contact etch stop layer formed in the contact hole trench.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a first top oxide layer and a silicon layer that is formed on the first top oxide layer. The structure further includes a plurality of rib waveguide components that are formed in the silicon layer. A first rib waveguide component of the plurality includes first contact holes having a first contact hole depth, and a second rib waveguide component of the plurality includes second contact holes having a second contact hole depth, such that the depths of the first contact hole and the second contact hole are different.

Abstract: A photonic device, structure, and fabrication method that includes a substrate having a topside oxide layer formed thereon. The structure also includes a silicon layer that is formed on the topside oxide layer, and one or more waveguide components that are formed in the silicon layer. In addition, the structure includes a reflection device trench structure that is formed in the silicon layer, and which includes a first oblique plane, a bottom plane, and a second oblique plane. The photonic structure also includes a reflection device that is formed adjacent to the first oblique plane, and which has a reflection device angle relative to the bottom plane and configured to direct light into a waveguide component.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a buffer layer on the substrate, forming a mesa isolation on the HEMT region, forming a HEMT on the mesa isolation, and then forming a capacitor on the capacitor region. Preferably, a bottom electrode of the capacitor contacts the buffer layer directly.

Abstract: This disclosure describes systems, methods, and devices related to service function chaining in wireless networks. A communications system may include a communication control function to select one or multiple communication service functions associated with establishing service function chaining (SFC) services for telecommunications; a service orchestration and chaining function (SOCF) to establish the SFC services; and a service orchestration exposure function (SOEF) to expose the SFC services to an application function (AF) of the system.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.

Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

Abstract: Various embodiments of the present disclosure are directed to a vertical gate-all-around (GAA) memory cell. A middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. An insulator structure is between the lower conductor and the middle conductor. A semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.

Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).

Abstract: A self-healing resin composition and a self-healing membrane structure are provided. The self-healing resin composition includes 20 phr to 50 phr of a self-healing resin, 1 phr to 10 phr of a hardener, 0.1 phr to 3 phr of a matting agent, and 40 phr to 80 phr of a solvent. The self-healing resin is polymerized from a polyester polyol, a diisocyanate monomer, and a bisphenol monomer. A molar ratio of a hydroxyl group to an isocyanate group in monomers to polymerize the self-healing resin ranges from 1.33 to 2.0. A number average molecular weight of the self-healing resin ranges from 30,000 g/mol to 200,000 g/mol.

Abstract: Various embodiments herein provide techniques to enable communication between a user equipment (UE) microservice and a microservice of a wireless cellular network via service mesh. A first solution is described, in which the service mesh is in the network, and the network includes a service mesh proxy to communicate with the UE. A second solution is also described, in which the UE is part of the cellular network service mesh and includes a service mesh proxy in the UE. Other embodiments may be described and claimed.

Abstract: Technology for an Information Centric Networking gateway (ICN-GW) operable to modify an ICN message received from a user equipment (UE) in a Fifth Generation (5G) cellular network is disclosed. The ICN-GW can decode the ICN message received from the UE via a Next Generation NodeB (gNB) and an ICN point of attachment (ICN-PoA). The ICN-GW can modify the ICN message to produce a modified ICN message. The ICN-GW can encode the modified ICN message to route the modified ICN message to a data network.