Patents by Inventor Yu-Lin Hsiao

Yu-Lin Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240097888
    Abstract: In a file sharing system, a key manager unit realizes a correspondence between the first user identifier and the first public key in response to a registration request of the first user, generates a first key material for encrypting the first file into a first encrypted file, and generates a first credential according to the first user identifier, the first file identifier, the first public key and the first key material after receiving an access-right claim request to the first file from the first user. A file storage unit stores the first encrypted file and the first credential. The first user uses the first user identifier, the first file identifier and the first private key to retrieve the first key material out of the first credential, and uses the first key material to decrypt the first encrypted file into the first file.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 21, 2024
    Inventors: CHIA-JUNG LIANG, CHIHHUNG LIN, CHIH-PING HSIAO, YU-JIE SU, CHIA-HSIN CHENG, TUN-HOU WANG, MENG-CHAO TSAI, YUEH-CHIN LIN
  • Patent number: 11797442
    Abstract: An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: October 24, 2023
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventors: Zhong-Ho Chen, Yu-Lin Hsiao, Hsin Ming Chen
  • Publication number: 20230122423
    Abstract: An integrated circuit and a method for executing a cache management operation are provided. The integrated circuit includes a master interface, a slave interface, and a link. The link is connected between the master interface and the slave interface, and the link includes an A-channel, a B-channel, a C-channel, a D-channel, and an E-channel. The A-channel is configured to transmit a cache management operation message of the master interface to the slave interface, and the cache management operation message is configured to manage data consistency between different data caches. The D-channel is configured to transmit a cache management operation acknowledgement message of the slave interface to the master interface.
    Type: Application
    Filed: October 18, 2021
    Publication date: April 20, 2023
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventors: Zhong-Ho Chen, Yu-Lin Hsiao, Hsin Ming Chen
  • Patent number: 10418240
    Abstract: A nitride semiconductor structure includes a substrate, a nitride semiconductor layer, and a buffer stack layer between the substrate and the nitride semiconductor layer. The buffer stack layer includes a plurality of metal nitride multilayers repeatedly stacked, wherein each of the metal nitride multilayers consists of a first, a second, and a third metal nitride thin films in sequence, or consists of the first, the third, the second, and the third metal nitride thin films in sequence. The aluminum concentration of the first metal nitride thin film is higher than that of the third metal nitride thin film, and the aluminum concentration of the third metal nitride thin film is higher than that of the second metal nitride thin film.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 17, 2019
    Assignee: ELITE ADVANCED LASER CORPORATION
    Inventors: Kun-Chuan Lin, Jin-Hsiang Liu, Yu-Lin Hsiao
  • Publication number: 20190198406
    Abstract: A substrate includes a substrate body and an interconnection layer disposed on a bearing surface of the substrate body and having an annular portion and a plurality of protrusions extending outward from an outer periphery of the annular portion. A package module is formed by the substrate, a chip mounted on the bearing surface of the substrate body, and a cap enclosing the chip and having a bottom thereof adhered to the interconnection layer of the substrate by an adhesive. By means of the protrusions of the interconnection layer, the bonding area of the adhesive is increased and the spread of the adhesive is effectively concentrated.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 27, 2019
    Inventors: Yu-Shiang CHEN, Chao-Wei YU, Yu-Lin HSIAO, Ming-Te TU
  • Patent number: 10312169
    Abstract: A substrate includes a substrate body and an interconnection layer disposed on a bearing surface of the substrate body and having an annular portion and a plurality of protrusions extending outward from an outer periphery of the annular portion. A package module is formed by the substrate, a chip mounted on the bearing surface of the substrate body, and a cap enclosing the chip and having a bottom thereof adhered to the interconnection layer of the substrate by an adhesive. By means of the protrusions of the interconnection layer, the bonding area of the adhesive is increased and the spread of the adhesive is effectively concentrated.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 4, 2019
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Yu-Shiang Chen, Chao-Wei Yu, Yu-Lin Hsiao, Ming-Te Tu
  • Publication number: 20190157080
    Abstract: A nitride semiconductor structure includes a substrate, a nitride semiconductor layer, and a buffer stack layer between the substrate and the nitride semiconductor layer. The buffer stack layer includes a plurality of metal nitride multilayers repeatedly stacked, wherein each of the metal nitride multilayers consists of a first, a second, and a third metal nitride thin films in sequence, or consists of the first, the third, the second, and the third metal nitride thin films in sequence. The aluminum concentration of the first metal nitride thin film is higher than that of the third metal nitride thin film, and the aluminum concentration of the third metal nitride thin film is higher than that of the second metal nitride thin film.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 23, 2019
    Applicant: ELITE ADVANCED LASER CORPORATION
    Inventors: Kun-Chuan Lin, Jin-Hsiang Liu, Yu-Lin Hsiao
  • Patent number: 10287386
    Abstract: The present invention is related to a core-shell particle and preparation and use thereof. The core of the core-shell particle includes a vinyl polymer. The shell of the core-shell particle includes a hydrophobic silane bonded to a surface of the core via a silane coupling agent. The core-shell particles are applied in a matting material as a matting agent.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Eternal Materials Co., Ltd.
    Inventors: Yu-Huei Su, Yu-Lin Hsiao, Wen-Yen Chiu, Chi-An Dai, Chen-Han Yang, Bo-Ting Chou
  • Publication number: 20190031807
    Abstract: The present invention is related to a core-shell particle and preparation and use thereof. The core of the core-shell particle includes a vinyl polymer. The shell of the core-shell particle includes a hydrophobic silane bonded to a surface of the core via a silane coupling agent. The core-shell particles are applied in a matting material as a matting agent.
    Type: Application
    Filed: July 28, 2017
    Publication date: January 31, 2019
    Inventors: Yu-Huei Su, Yu-Lin Hsiao, Wen-Yen Chiu, Chi-An Dai, Chen_Han Yang, Bo-Ting Chou
  • Patent number: 8536616
    Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: September 17, 2013
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Yu-Lin Hsiao, Jung-Chi Lu
  • Publication number: 20120298991
    Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
    Type: Application
    Filed: August 9, 2012
    Publication date: November 29, 2012
    Applicant: National Chiao Tung University
    Inventors: Edward Yi Chang, Yu-Lin Hsiao, Jung-Chi Lu
  • Patent number: 8263425
    Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 11, 2012
    Assignee: National Chiao Tung University
    Inventors: Edward Yi Chang, Yu-Lin Hsiao, Jung-Chi Lu
  • Publication number: 20120097968
    Abstract: The present invention provides a method for forming a multilayer substrate having a gallium nitride layer, wherein a mesh layer having a plurality of openings is formed on a substrate, and a buffer layer, three aluminum gallium nitride layers with different aluminum concentrations and a gallium nitride layer are formed in sequence on the substrate in the openings. The three aluminum gallium nitride layers with different aluminum concentrations are capable of releasing stress, decreasing cracks on the surface of the gallium nitride layer and controlling interior defects, such that the present invention provides a gallium nitride layer with larger area, greater thickness, no cracks and high quality for facilitating the formation of high performance electronic components in comparison with the prior art. The present invention further provides a multilayer substrate having a gallium nitride layer.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 26, 2012
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Edward Yi Chang, Yu-Lin Hsiao, Jung-Chi Lu