Patents by Inventor Yu-Lin Kao

Yu-Lin Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979158
    Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
  • Publication number: 20240144890
    Abstract: A backlight control circuit for a surface light emitting device is provided. The backlight control circuit includes a driving circuit. The driving circuit is configured to generate a plurality of driving currents to drive the surface light emitting device such that a plurality of backlight blocks of the surface light emitting device generate a plurality of brightness values. The surface light emitting device is divided into a first backlight area and a second backlight area. The second backlight area is closer to an edge of the surface light emitting device than the first backlight area. A first driving current of the plurality of driving currents is utilized for driving the light source of the first backlight area. A second driving current of the plurality of driving currents is utilized for driving the light source of the second backlight area. The second driving current is greater than the first driving current.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Applicant: Radiant Opto-Electronics Corporation
    Inventors: Li-Fei Wang, Yu-Lin Hsieh, Sheng-Kai Fang, Pei-Ling Kao
  • Publication number: 20230142264
    Abstract: Embodiments are directed to an electronic device that includes a cover and a haptic module positioned below the cover. The haptic module includes a substrate positioned below the cover and offset from the cover, a spacer positioned between the substrate and the cover and coupling the substrate to the cover, and a piezoelectric element positioned on a surface of the substrate and offset from the cover to define a gap between the piezoelectric element and the cover. The electronic device can also include a sensor coupled to the cover and configured to detect an input, and a processing unit operably coupled to the piezoelectric element and configured to cause the piezoelectric element to deflect the cover in response to the sensor detecting the input.
    Type: Application
    Filed: August 30, 2022
    Publication date: May 11, 2023
    Inventors: Alex J. Lehmann, Joonas I. Ponkala, Keith J. Hendren, Xian Wang, Yu-Lin Kao, Kevin C. Armendariz
  • Publication number: 20230068435
    Abstract: Semiconductor die assemblies with sidewall protection, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die with a low-k dielectric layer and a stack of semiconductor dies attached to the interface die. The semiconductor die assembly also includes a molding structure that protects sidewalls of the interface die and sidewalls of the semiconductor dies. In some embodiments, the semiconductor die assembly includes a passivation layer attached to the interface die opposite to the stack of semiconductor dies. Further, the passivation layer may include a sidewall surface coplanar with an outer sidewall surface of the molding structure. The passivation layer may include a ledge underneath the molding structure, which is uncovered by the interface die. The semiconductor die assembly may include a NCF material at the sidewalls of the stack of semiconductor dies, where the molding structure surrounds the NCF material.
    Type: Application
    Filed: February 9, 2022
    Publication date: March 2, 2023
    Inventors: Yu Lin Kao, Chun Min Lin, Sui Chi Huang, Pei Sian Shao
  • Patent number: 10064768
    Abstract: A Y-type gauze positioning rod is adapted to be disposed in a Y-type gauze so as to position the Y-type gauze to an affected region. The Y-type gauze positioning rod includes a Y-type flexible body having a holder and two supporting branches. The two supporting branches are connected to the holder and separated from each other. A Y-type gauze positioning assembly is further provided.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 4, 2018
    Assignee: I-SHOU UNIVERSITY
    Inventors: Yu-Lin Kao, Yu-Shiuan Zheng, Nien-Hsun Lin, Yu-Ting Wu, Pei-Rung Liu, Pei-Hsing Tseng, Yu-Han Huang, Han-Chun Liu, Yu-Hua Lin, Chia-Chan Kao
  • Publication number: 20170312150
    Abstract: A Y-type gauze positioning rod is adapted to be disposed in a Y-type gauze so as to position the Y-type gauze to an affected region. The Y-type gauze positioning rod includes a Y-type flexible body having a holder and two supporting branches. The two supporting branches are connected to the holder and separated from each other. A Y-type gauze positioning assembly is further provided.
    Type: Application
    Filed: February 13, 2017
    Publication date: November 2, 2017
    Applicant: I-SHOU UNIVERSITY
    Inventors: Yu-Lin Kao, Yu-Shiuan Zheng, Nien-Hsun Lin, Yu-Ting Wu, Pei-Rung Liu, Pei-Hsing Tseng, Yu-Han Huang, Han-Chun Liu, Yu-Hua Lin, Chia-Chan Kao
  • Patent number: 8383881
    Abstract: A method for producing polyploid plants of orchids includes the steps of: providing a protocorm or protocom-like body (PLB) of an orchid, the protocorm or PLB having an upper portion with a growing point and a lower portion without any growing point; cutting the protocorm or PLB approximately at a point of half height to separate the upper portion; subculturing the lower portion of the protocorm or PLB in an inducing medium, and putting a cut surface of the lower portion of the protocorm or PLB to face upward so that one or more next-generation PLBs grow from the cut surface of the lower portion. The method characterized in using no antimicrotubule agent can simplify the entire process of orchid polyploidy breeding, and can be used in mass-production of the stable polyploid plants.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: February 26, 2013
    Assignee: National University of Kaohsiung
    Inventors: Wen-Huei Chen, Yu-Lin Kao, Ching-Yan Tang
  • Publication number: 20090176227
    Abstract: A method for producing polyploid plants of orchids includes the steps of: providing a protocorm or protocom-like body (PLB) of an orchid, the protocorm or PLB having an upper portion with a growing point and a lower portion without any growing point; cutting the protocorm or PLB approximately at a point of half height to separate the upper portion; subculturing the lower portion of the protocorm or PLB in an inducing medium, and putting a cut surface of the lower portion of the protocorm or PLB to face upward so that one or more next-generation PLBs grow from the cut surface of the lower portion. The method characterized in using no antimicrotubule agent can simplify the entire process of orchid polyploidy breeding, and can be used in mass-production of the stable polyploid plants.
    Type: Application
    Filed: October 22, 2008
    Publication date: July 9, 2009
    Inventors: Wen-Huei Chen, Yu-Lin Kao, Ching-Yan Tang