Abstract: A display device includes a multiple of light-emitting elements and a multiple of driving circuits. Each of the multiple of driving circuits is configured to generate a driving current flowing through one of the multiple of light-emitting elements. Each of the multiple of driving circuits includes a first transistor, a second transistor, a reset circuit, a first control circuit and a second control circuit. The driving current flows from a first system high voltage terminal through the first transistor, the second transistor and one of the multiple of light-emitting elements to a system low voltage terminal. The first control circuit is configured to control the first transistor to modulate pulse amplitude of the driving current. The second control circuit is configured to control the second transistor to modulate pulse width of the driving current.

Abstract: The present invention provides a memory structure, which is disposed on a first circuit board and connected electrically to a system power supply of a second circuit board. The memory structure comprises a plurality of memory unit, a power control component, and a display component. The power control component receives a first voltage of the system power supply. The power control component includes a power management unit and a linear voltage stabilizing unit. The display component includes a light-emitting unit and a control unit. The power control component provides a second voltage to the plurality of memory units using the power management unit. The linear voltage stabilizing unit provides a third voltage to the light-emitting unit and the control unit. The power management unit distributes the power supply to the plurality of memory units, the light-emitting unit, and the control unit for further usage.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A semiconductor structure includes a channel layer, a top source/drain feature, a bottom source/drain feature, a gate structure, and a supporting structure. The channel layer extends in a Z-direction. The top source/drain feature is over and electrically connected to the channel layer. The bottom source/drain feature is under and electrically connected to the channel layer. The gate structure laterally wraps around the channel layer. The supporting structure extends in an X-direction. The supporting structure is in contact with the channel layer, the top source/drain feature, and the bottom source/drain feature in a Y-direction.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a channel layer extending along a vertical direction, and a top S/D structure formed on the channel layer. The semiconductor structure also includes a bottom S/D structure formed below the channel layer, and a gate structure adjacent to the channel layer. The channel layer is surrounded by the gate structure. The semiconductor structure includes a top inner spacer layer formed on the gate structure, and a top surface of the channel layer is higher than a bottom surface of the top inner spacer layer.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in a packaging layer, and a circuit structure is formed on the packaging layer and electrically connected to the first electronic element and the second electronic element, where the circuit structure has a heat dissipation portion thermally connected to the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation portion, so as to avoid the problem of affecting the operation of the second electronic element due to overheating of the packaging layer.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a first electronic element and a second electronic element are embedded in an encapsulation layer, and a circuit structure is disposed on the encapsulation layer and electrically connected to the first electronic element and the second electronic element. The circuit structure has a hollow area corresponding to the first electronic element, and a heat dissipation structure is disposed in the hollow area to thermally connect the first electronic element. Therefore, the heat energy generated by the first electronic element can be quickly dissipated to the outside via the heat dissipation structure, so as to avoid the problem of affecting the operation of the second electronic element due to the overheating of the encapsulation layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: In an embodiment, a device includes: a lower source/drain region; an upper source/drain region; a nanostructure between the upper source/drain region and the lower source/drain region; a gate structure extending into a sidewall of the nanostructure, the gate structure including a gate dielectric and a gate electrode, an outer sidewall of the gate electrode being aligned with an outer sidewall of the gate dielectric; and a gate contact adjacent the gate structure, the gate contact extending along the outer sidewall of the gate electrode and the outer sidewall of the gate dielectric.

Abstract: This document describes techniques and systems that enable a range extender device. The techniques and systems include a user device that includes a housing with an audio sensor, a heat sink assembly, a circuit board assembly, and a speaker assembly positioned within the housing. The housing includes a top housing member connected to a bottom housing member. The top housing member includes a concave-down top-end portion connected to a generally-cylindrical vertical wall via rounded corners. The heat sink assembly includes a heat sink and one or more antennas positioned proximate to an inner surface of the vertical wall. The circuit board assembly is positioned within the housing and proximate to the heat sink assembly, and the speaker assembly is positioned within the housing and connected to the circuit board assembly. Also, a light ring assembly is connected to a bottom exterior surface of the bottom housing member.

Abstract: This disclosure relates to techniques for a wireless device to perform millimeter wavelength communication with increased reliability and power efficiency using sensor inputs. The sensor inputs may include motion, rotation, or temperature measurements, among various possibilities. The sensor inputs may be used when performing beamforming tracking, antenna configuration, transmit and receive chain measurements and selection, and/or in any of various other possible operations.

Abstract: A method of building upstream-and-downstream configuration of sensors includes determining two sets of geographic position data of a target sensor and a candidate sensor, obtaining pollution-associated periods according to pieces of flow field data, the sets of geographic position data and pieces of target sensing data of the target sensor to determine a pollution-associated period, calculating a correlation between target sensing data obtained by the target sensor during the pollution-associated period and candidate sensing data obtained by the candidate sensor during the associated air pollution period to obtain sensor correlations, and determining the target sensor and the candidate sensor having a upstream-and-downstream relationship with the candidate sensor being used as a satellite sensor of the target sensor when a quantity ratio of sensor correlations being larger than or equal to a correlation threshold is larger than or equal to a default ratio.

Abstract: A sensing cell includes: a first electrode coupled to a gate of a transistor, a second electrode spaced apart from the first electrode; a protective layer covering sidewalls of the first electrode and the second electrode and having a first opening and a second opening exposing a first part of the first electrode and a second part of the second electrode, respectively; a first well located on the protective layer and surrounding the first electrode and the second electrode and having a third opening exposing the first part of the first electrode, the second part of the second electrode, and the protective layer between the first opening and the second opening; a second well located on the protective layer surrounding the first well and having a fourth opening to limit a flow of a liquid to be tested; and an ion selective membrane located in the third opening.

Abstract: Provided is a coronavirus detection method which is suitable for a coronavirus disease 2019 (COVID-19) detection. The method includes the following steps. A field-effect transistor-based biosensor (BioFET) platform is provided, wherein the BioFET platform includes a BioFET and a sensor card. The sensor card is detachably connected to the BioFET, wherein the sensor card includes a plurality of sensors and each of the plurality of sensors includes a response electrode. A nucleic acid probe specific to a nucleic acid sequence of COVID-19 virus is immobilized on a surface of the response electrode. A test solution is placed on the response electrode of the sensor card. A pulse voltage is applied to the response electrode, and a detection current generated from the sensor card is measured.

Abstract: A sensing device is provided. The sensing device includes a transistor, a disposable electrode, and a remote electrode. The transistor includes an extended gate, source and drain. The remote electrode is configured to receive a reference voltage. The disposable electrode is coupled between the transistor and the remote electrode. The disposable electrode includes a proximal end and a distal end. The proximal end of the disposable electrode is coupled to the extended gate of the transistor. The distal end of the disposable electrode is coupled to the remote electrode. The disposable electrode is adapted to load a cell and receive a membrane potential of the cell. The disposable electrode provides a gate voltage to the extended gate based on the change of the membrane potential and the reference voltage. The transistor provides different transistor currents at the drain based on the change of the gate voltage.

Abstract: A fluid quality tracing method includes obtaining pieces of fluid concentration distribution data of a detected region corresponding to detection time points respectively, generating pieces of concentration grid data respectively according to the pieces of fluid concentration distribution data, obtaining pieces of fluid moving data of the detected region corresponding to the detection time points respectively, obtaining estimated positions according to the fluid moving data and an initial position, and creating a fluid concentration trajectory according to the pieces of concentration grid data, the initial position and the estimated positions. The initial position and the estimated positions are located in the detected region. The fluid concentration trajectory includes line segments with terminals corresponding to the initial position and the estimated positions respectively, and the line segments indicate concentration representative values respectively.