Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: A solid-state lithium battery includes a solid electrolyte layer, a first electrode layer structure, a second electrode layer structure, a first collector layer and a second collector layer. The first electrode layer structure includes a first buffer electrolyte layer and a first microporous electrode layer. The first buffer electrolyte layer is located between the first microporous electrode layer and the first surface of the solid electrolyte layer. The first buffer electrolyte layer is embedded with the first surface of the solid electrolyte layer. The second electrode layer structure is disposed on the second surface of the solid electrolyte layer. The first microporous electrode layer is disposed between the first collector layer and first buffer electrolyte layer. The second electrode layer structure is disposed between the second collector layer and the second surface of the solid electrolyte layer.

Abstract: A method of manufacturing a snapback electrostatic discharge (ESD) protection circuit includes fabricating a first well in a substrate, the first well extending in a first direction, and having a first dopant type, fabricating a drain region of a transistor in the first well, the drain region having a second dopant type, fabricating a source region of the transistor in the first well, the source region extending in the first direction, having the second dopant type, and being separated from the drain region in a second direction, fabricating a second well in the first well, the second well extending in the first direction, having the second dopant type, and being adjacent to a portion of the drain region, and fabricating a gate region of the transistor, the gate region being between the drain region and the source region, and being over the first well and the substrate.

Abstract: A display control system for controlling a display panel having a plurality of display zones includes a main controller, a plurality of display driver circuits and a plurality of memories. Each of the display driver circuits is coupled to a corresponding display zone among the plurality of display zones, to control the corresponding display zone. Each of the memories is coupled to a corresponding display driver circuit among the plurality of display driver circuits, to store a compensation data for the corresponding display zone controlled by the corresponding display driver circuit. The plurality of display driver circuits are cascaded through a plurality of first transmission channels and connected through at least one second transmission channel, and each of the first transmission channels is coupled between two of the plurality of display driver circuits or between one of the plurality of display driver circuits and the main controller.

Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.

Abstract: A high-frequency transmission element is provided. The high-frequency transmission element includes a connecting wire structure and an impedance matching plate structure. The connecting wire structure includes a connecting wire and a connecting pad. The connecting pad is located at an end of the connecting wire. The impedance matching plate structure includes an impedance matching plate body, an opening, and an impedance matching portion. The connecting pad is located in a projection range of the opening in a direction of orthographic projection of the impedance matching plate structure. The impedance matching portion is located in a periphery of the opening and extends in the direction from the connecting wire towards the connecting pad.

Abstract: Access to emails delivered to an employee of an enterprise is received. An incoming email addressed to the employee is acquired. A primary attribute is extracted from the incoming email by parsing at least one of: (1) content of the incoming email or (2) metadata associated with the incoming email. It is determined whether the incoming email deviates from past email activity, at least in part by determining, as a secondary attribute, a mismatch between a previous value for the primary attribute and a current value for the primary attribute, using a communication profile associated with the employee, and providing a measured deviation to at least one machine learning model.

Abstract: A cooler having an optimized coating structure for an electric vehicle power module is provided. The cooler includes a metal cooling substrate and a coating structure. The coating structure has at least a barrier layer and a function layer. The barrier layer is formed on the metal cooling substrate. The barrier layer is a nickel coating layer or a nickel alloy coating layer having a thickness of between 0.1 ?m and 0.5 ?m. The function layer is a silver/silver alloy coating layer, or a copper/copper alloy coating layer having a thickness of between 0.1 ?m and 0.5 ?m.

Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

Abstract: The present invention provides an electrochemical unit, a manufacturing method for the same and a use of the same as a component of batteries, and an electrochemical device including the same. The electrochemical unit includes a mixture layer and a transition metal oxide layer. The mixture layer includes an oxide made of a first transition metal, an oxide made of a second transition metal, and a first alkali metal. The transition metal oxide layer is disposed on one side of the mixture layer, where the transition metal oxide layer includes a third transition metal oxide.

Abstract: A method for manufacturing a doped metal oxide film includes following steps. First, a substrate is provided. Second, a metal oxide film is formed on the substrate by using a capacitive pulsed arc plasma technique to control a metal ion film to be doped, and by integrating an arc plasma coating process or a physical vapor deposition process. The invention completes the in-situ doping function of metal oxides and compounds in a single process, and can be used for manufacturing functional components for continuous processes without breaking vacuum condition, and is applied to the thin film process of electrochemical components such as electrochromic devices or lithium batteries.

Abstract: The present invention provides an electrochemical unit, a manufacturing method for the same and a use of the same as a component of batteries, and an electrochemical device including the same. The electrochemical unit includes a mixture layer and a transition metal oxide layer. The mixture layer includes an oxide made of a first transition metal, an oxide made of a second transition metal, and a first alkali metal. The transition metal oxide layer is disposed on one side of the mixture layer, where the transition metal oxide layer includes a third transition metal oxide.

Abstract: A display panel comprises a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a first transparent conductive layer and a first alignment layer. The first transparent conductive layer includes a first surface and has at least a first notch, the first alignment layer includes a first part and a second part, the first part is disposed in the first notch, the second part is disposed on the first surface, and the surface roughness of the first part of the first alignment layer is greater than that of the second part. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. A display device having the display panel is also disclosed.

Abstract: A display panel includes a first substrate having a first alignment film, a second substrate having a second alignment film and plural spacers, a liquid crystal layer disposed between the first and second substrates, and a plurality of agglomerates positioned between the first and second alignment films and further surrounding at least one of the spacers. The spacers maintain a uniform gap between the first and second substrates. The second alignment film is disposed oppositely to the first alignment film and covers the spacers. In one embodiment, sizes of the agglomerates are distributed in a range of 0.1 ?m˜2 ?m.

Abstract: Disclosed are a method, a data processing engine, and a system for real-time processing a plurality of continuously-generated data streams. The method for real-time processing the data with different schemas that transmit from heterogeneous relational databases includes steps of identifying categories the data, converting the data, and then storing the data in a non-relational data. Moreover, an architecture is provided together with the system and the method to improve the management of products, product lines or lifecycle such as the feedback of information regarding the performance analysis of an online game, or real-time alerts and recommended actions regarding the yield rate in a manufacturing stage of an industry such as the semiconductor manufacturing industry.

Abstract: A display panel comprises a first substrate, a second substrate and a liquid crystal layer. The first substrate includes a first transparent conductive layer and a first alignment layer. The first transparent conductive layer includes a first surface and has at least a first notch, the first alignment layer includes a first part and a second part, the first part is disposed in the first notch, the second part is disposed on the first surface, and the surface roughness of the first part of the first alignment layer is greater than that of the second part. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. A display device having the display panel is also disclosed.

Abstract: A display panel comprises a first substrate having a first alignment film, a second substrate having a second alignment film and plural spacers, a liquid crystal layer disposed between the first and second substrates, and a plurality of agglomerates positioned between the first and second alignment films and further surrounding at least one of the spacers. The spaces maintain a uniform gap between the first and second substrates. The second alignment film is disposed oppositely to the first alignment film and covers the spacers. In one embodiment, sizes of the agglomerates are distributed in a range of 0.1 ?m˜2 ?m.